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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Transforming nanodevices to next generation nanosystems

Transforming nanodevices to next generation nanosystems

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Max Marcel Shulaker Gage Hills H.-S. Philip Wong Subhasish Mitra Deparment of Computer Science Stanford University Stanford CA USA

ISBN: (纸本)9781509030774

The computing demands of future data-intensive applications far exceed the capabilities of today's electronics, and cannot be met by isolated improvements in transistor technologies or integrated circuit (IC) architectures alone. Rather, transformative nano-systems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. For instance, monolithic three-dimensional integration enables revolutionary digital system architectures of computation finely immersed in memory. Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today's designs. While such systems are challenging to realize with conventional silicon-based technologies, they are naturally enabled by emerging nanotechnologies that can be fabricated at low processing temperatures. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors (CNFETs) and emerging memory technologies such as Resistive RAM (RRAM).

关键词： Three-dimensional displays Integrated circuits CNTFETs Silicon Energy efficiency Random access memory

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Performance and energy evaluation of spark applications on low-power SoCs

Performance and energy evaluation of spark applications on l...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ioannis Stamelos Dimitrios Soudris Christoforos Kachris Institute of Communication and Computer Systems (ICCS/NTUA) Athens Greece National Technical University of Athens (NTUA) Athens Greece

ISBN: (纸本)9781509030774

Microservers have recently gained attention as low-cost, low power, reduced footprint servers that are mainly based on energy efficient processors such as the ones used in embedded systems. Microservers based on low-power embedded processors are mainly targeting lightweight applications or parallel applications that benefit most from individual low-power servers with sufficient I/O between nodes rather than high performance processors. In this paper we evaluate the mapping of Apache Spark on low-power SoC-based processors. Apache Spark is one of the most widely framework in cloud computing for batch and streaming data analytics. We evaluate the energy efficiency of low-power SoCs that are used in embedded system for the execution of several Spark applications. The performance evaluation shows that low-power SoCs have the potential to offer up to 3x higher energy efficiency compared to high performance processors typically used in data centers.

关键词： Program processors Servers Sparks Hardware Programming Power demand Databases

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On the modeling of error functions as high dimensional landscapes for weight initialization in learning networks

On the modeling of error functions as high dimensional lands...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Julius Gopinath Mahale T. Sumana C. S. Adityakrishna Department of Physics BITS-Pilani Hyderabad India CAD Lab Indian Institute of Science India Department of Computer Science BITS-Pilani Hyderabad India

ISBN: (纸本)9781509030774

Next generation deep neural networks for classification hosted on embedded platforms will rely on fast, efficient, and accurate learning algorithms. Initialization of weights in learning networks has a great impact on the classification accuracy. In this paper we focus on deriving good initial weights by modeling the error function of a deep neural network as a high-dimensional landscape. We observe that due to the inherent complexity in its algebraic structure, such an error function may conform to general results of the statistics of large systems. To this end we apply some results from Random Matrix Theory to analyse these functions. We model the error function in terms of a Hamiltonian in N-dimensions and derive some theoretical results about its general behavior. These results are further used to make better initial guesses of weights for the learning algorithm.

关键词： Training Mathematical model Eigenvalues and eigenfunctions Neurons Artificial neural networks Biological neural networks

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Algorithms and architectures for parallel processing: ICA3PP 2016 collocated workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS Granada, Spain, December 14-16, 2016 proceedings 16th

Algorithms and architectures for parallel processing: ICA3PP...

引用

16th international conference on Algorithms and architectures for Parallel Processing - ICA3PP 2016 Collocated Workshops: 1st Workshop on Supercomputing Co-Design Technology, SCDT-2016, 1st international Workshop on Theoretical Approaches to Performance Evaluation, modeling and simulation, TAPEMS 2016, 1st international Workshop on Trust, Security and Privacy for Big Data, BigTrust 2016, 1st edition of the workshop on Ultrascale Computing for Early Researchers, UCER 2016 and 1st international Workshop on Data Locality in Modern Computing systems, DLMCS 2016

作者： Carretero, Jesus

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Static cost estimation for data layout selection on GPUs 7

Static cost estimation for data layout selection on GPUs

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7th international Workshop on Performance modeling, Benchmarking and simulation of High Performance Computing systems, PMBS 2016

作者： Peng, Yuhan Grossman, Max Sarkar, Vivek Department of Computer Science Rice University HoustonTX77005 United States

ISBN: (纸本)9781509052189

Performance modeling provides mathematical models and quantitative analysis for designing and optimizing computer systems. In high performance architectures, high-latency memory accesses often dominate execution time in many classes of applications. Thus, performance modeling for memory accesses of high performance architectures has been an important research topic. In high performance computation, data layout can significantly affect the efficiency of memory access operations. In recent years, the problem of data layout selection has been well studied on various parallel CPU and some GPU architectures. GPUs have memory hierarchies different from multi-core CPUs. While data layout selection on GPUs has been inspected by several existing projects, there is still a lack of a mathematical cost model for data layout selection on GPUs. This motivates us to investigate static cost analysis methods that could better guide future data layout selection work, and perhaps even designing new SIMT *** this paper, we propose a comprehensive cost analysis for data layout selection for GPUs. We build our cost function based on the knowledge of the GPU memory hierarchy, and develop an algorithm which allows researchers to perform compile time cost estimation for a given data layout. Furthermore, we introduce a new vector based representation to represent the estimated cost, which can better estimate the cost of applications with dynamic length loops. We apply our cost analysis to selected benchmarks from past publications on data layout selection. Our experimental results show that our cost analysis can accurately predict the relative costs of different data layouts. Using the cost model presented in this paper, we are developing an automatic data layout selection tool in our ongoing work. © 2016 IEEE.

关键词： Graphics processing unit

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Processes and actors: Translating Kahn processes to dataflow with firing

Processes and actors: Translating Kahn processes to dataflow...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Gustav Cedersjö Jörn W. Janneck Department of Computer Science Lund University Sweden

Dataflow programming is a paradigm for describing stream processing algorithms in a manner that naturally exposes their concurrency and makes the resulting programs readily implementable on highly parallel architectures. Dataflow programs are graph structured, with nodes representing computational kernels that process the data flowing over the edges. There are two major families of languages for the kernels: process languages and languages for dataflow with firing. While processes tend to be easier to write, the additional structure provided by the dataflow-with-firing style increases the analyzability of dataflow programs and supports more efficient implementation techniques. This paper seeks to combine these benefits in a principled manner by constructing a family of translations from a process language to dataflow with firing. In order to formally relate these descriptions, we first introduce a notion of firing to the semantics of Kahn processes, which allows us to give a precise definition of equivalence between programs written in these different styles. Then we introduce a family of translations between them and and show that they retain meaning of a program. The presented language and its translation has been implemented in a compiler for the dataflow programming language CAL.

关键词： Semantics Ports (computers) Computational modeling Structural rings Grammar Programming computer languages

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Concurrent memory subsystem and application optimization for ASIP design

Concurrent memory subsystem and application optimization for...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Juan Fernando Eusse Francisco Fernandez Rainer Leupers Gerd Ascheid Institute for Communication Technologies and Embedded Systems (ICE) RWTH Aachen University Germany

ISBN: (纸本)9781509030774

The design of an adequate memory subsystem is critical for the achievement of high performance in application specific and data plane processors. Applications running on such processors must fully exploit the memory hierarchy, so that the gains achieved due to hardware optimization are not invalidated by software inefficiency. This paper presents a framework that vertically integrates the process of memory subsystem design with application optimization and algorithmic exploration. Based on an abstract model, the framework is able to predict the impact that a customization in the memory hierarchy will have on performance, while applying optimization techniques to efficiently utilize it. To perform the aforementioned processes, the tool flow relies on source level information and a novel data model, avoiding the necessity for expensive cycle-accurate simulations. Throughout the evaluation, we show that the framework is capable of predicting memory-related performance metrics with an accuracy of ±10%, when compared to simulation. Furthermore, we show that the approach is significantly more efficient than simulation, and can lead to gains in designer's productivity up to a factor of 40x.

关键词： Program processors Estimation Optimization Algorithm design and analysis Cache memory Clocks Prediction algorithms

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Modelling and simulation of optical integrated networks for early-stage design exploration (WIP) 48

Modelling and simulation of optical integrated networks for ...

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48th Summer computer simulation conference, SCSC 2016, Part of the 2016 Summer simulation Multi-conference, SummerSim 2016

作者： Odile, Liboiron-Ladouceur De Magalhaes, Felipe Gohring Hessel, Fabiano Nicolescu, Gabriela Ecole Polytechnique de Montreal -PPGCC/PUCRS Montreal Canada PPGCC/PUCRS Porto Alegre Brazil McGill University Montreal Canada Ecole Polytechnique de Montreal Montreal Canada

ISBN: (纸本)9781510824256

Electrical interconnects will reach their physical limitations as we scale down components on systems' designs. At the same time, the demand for high throughput communication architectures rises. Optical integrated networks (OIN) are currently considered to be one of the most promising paradigm in this design context: They present high bandwidth and low power consumption. Such communication infra-structures lack currently a fast and reliable modelling method, which eases their development. In this context, this paper presents a modelling strategy and simulation tool for OIN-based systems, where the deployment of systems is performed entirely through a Graphical User Interface (GUI). © 2016 Society for modeling & simulation international (SCS).

关键词： Graphical user interfaces

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Black box ESL power estimation for loosely-timed TLM models

Black box ESL power estimation for loosely-timed TLM models

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Gereon Onnebrink Rainer Leupers Gerd Ascheid Stefan Schürmans Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Silexica Software Solutions GmbH Aachen Germany

ISBN: (纸本)9781509030774

Design space exploration (DSE) at system level needs to cover all parameters and has to find the best trade-off between performance and power of modern heterogeneous multi- and many-processor SoCs (MPSoC). Modelling virtual platforms with SystemC TLM offers fast HW and SW co-design using the loosely-timed (LT) coding style. However, simulations at this high abstraction level lack the capability of providing power estimates in case no insight into the models of the virtual platform is possible. This paper extends a well-proven black box power estimation methodology. The proposed method is capable of estimating the power with high accuracy using fast LT modelling. Two case studies reveal average estimation errors of just 5.1% and 3.5% for the ARM Cortex-A9 on the PandaBoard and the Blackfin 609 DSP on the FinBoard, respectively.

关键词： Estimation Encoding Program processors Timing Power demand Mathematical model Hardware

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XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation

XL-STaGe: A cross-layer scalable tool for graph generation, ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Pedro Campos Nizar Dahir Colin Bonney Martin Trefzer Andy Tyrrell Gianluca Tempesti Department of Electronics University of York York UK

ISBN: (纸本)9781509030774

This paper presents XL-STaGe, a cross-layer tool for traffic-inclusive directed acyclic graph generation and implementation. In contrast to other graph-generation tools which focus on high-level DAG models, XL-STaGe consists of a set of processes that generate the task-graphs as well as a detailed process model for each node in each graph. The tool is highly customizable, with many parameters that can be tuned to meet the user's requirements to control the topology, connection density, degree of parallelism and duration the task-graph. Moreover, two use cases are presented, a high-level one, which illustrate the benefit of the developed tool in application mapping and a circuit-level one to verify the accuracy of the XL-STaGe process models when implemented in hardware.

关键词： Solid modeling Instruction sets Throughput US Department of Transportation Parallel processing Computational modeling Hardware

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