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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Parallel Computing Education Through simulation 16th

Parallel Computing Education Through Simulation

引用

Joint conference of the 16th Asia simulation conference / SCS international Autumn simulation Multi-conference (AsiaSim/SCS AutumnSim)

作者： Wan, Han Luo, Xiaoyan Gao, Xiaopeng Long, Xiang Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Beihang Univ Sch Astronaut Beijing Peoples R China

ISBN: (纸本)9789811026638;9789811026621

With the advent of parallel computing, CS departments must face the question of how to integrate the parallel computing knowledge into the curricula. In this paper, we introduced our practice in the parallel computing education which used simulation methodology. In our course, students learned the basics of GPU architectures, parallel computing along with optimization techniques to tuning the performance. Furthermore, we elaborated the work which combined simulation-based architecture research and parallel computing - a cache simulator based on GPU. In this part, the common architecture research methodology with tool, such as simulation methodology and Pin tool were introduced. This study case has shown as an effective supplement to our teaching philosophy: balance design based on quantitative characterization.

关键词： Parallel computing education Architecture and organization course Curriculum design Practice

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Hardware-In-the-Loop simulation of UAV Hexacopter for Chemical Hazard Monitoring Mission 6

Hardware-In-the-Loop Simulation of UAV Hexacopter for Chemic...

引用

6th international conference on System Engineering and Technology (ICSET)

作者： Wandarosanza, Rendy Trilaksono, Bambang Riyanto Hidayat, Egi Inst Teknol Bandung Dept Elect Engn Jl Ganesha 10 Bandung 40132 West Java Indonesia

ISBN: (纸本)9781509050895

Field trial is a very critical stage and high risk in UAV development cycle. HILS is a computer-assisted simulation techniques used in the development and testing of complex embedded real-time systems. HILS has the ability to simulate UAV flight characteristics, sensor modeling, and modeling of actuators while communicating in real time with flight control hardware. HILS aims to test the reliability of UAV flight control hardware, integration test of Chemical monitoring systems, and tuning the control parameters. Advantages of using HILS are lower the development costs, improve safety, and streamline the development process. HILS provides development process without using actual UAV platform, but by using a mathematical equation to represent the UAV platform that will be used. HILS implement control system on Pixhawk then the output actuators used as model input. Hexacopter model will produce the attitude and position of hexacopter modeled as sensors model. The output of sensors model will be the input for computing the next control command of Pixhawk. HILS can be used to test the integration of UAV platform with Chemical sensor module to ensure Chemical monitoring missions can run well on the real situation.

关键词： Chemical Hazard Monitoring Hardware-In-The-Loop simulation Hexacopter Unmanned Air Vehicle

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A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures

A framework for exploring alternative fault-tolerant schemes...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Kostas Siozios Ioannis Savidis Dimitrios Soudris School of Electrical and Computer Engineering National Technical University of Athens Athens Greece Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA

ISBN: (纸本)9781509030774

For decades computer architects pursued one primary goal: performance. Transistor scaling has translated into remarkable gains in operating frequency and reduction in power consumption. However, increased complexity from the device to architecture levels impose several new challenges, including a decrease in dependability/reliability due to physical failures. Reconfigurable platforms are highly susceptible to scaling related complexity, typically resulting in higher power consumption as compared to application-specific integrated circuits. The concern becomes far more important in the 3-D integrated circuit (IC) domain as vertically stacked blocks exhibit increased thermal resistance to the heat sink. The degradation in dependability becomes an important design challenge, not only for safety critical systems, but for the majority of architectures. In this paper, a framework used to explore alternative fault-tolerant schemes is proposed that masks the degradation in reliability for 3-D FPGA platforms. simulation results at the RTL level highlight the benefits of the introduced solution, as the maximum operating frequency and power consumption are improved by 33% and 26%, respectively, as compared to similar state-of-the-art solutions.

关键词： Field programmable gate arrays Through-silicon vias Fault tolerant systems Fault tolerance Routing Tunneling magnetoresistance

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An Overview of simulation-Oriented Model Reuse 16th

An Overview of Simulation-Oriented Model Reuse

引用

Joint conference of the 16th Asia simulation conference / SCS international Autumn simulation Multi-conference (AsiaSim/SCS AutumnSim)

作者： Liu, Ying Zhang, Lin Zhang, Weicun Hu, Xiaolin Beihang Univ Sch Automat Sci & Elect Engn Beijing 100191 Peoples R China Minist Educ Engn Res Ctr Complex Prod Adv Mfg Syst Beijing 100191 Peoples R China Univ Sci & Technol Beijing Sch Automat & Elect Engn Beijing 100083 Peoples R China Georgia State Univ Dept Comp Sci Atlanta GA 30314 USA

ISBN: (纸本)9789811026720;9789811026713

simulation-oriented model reuse (SOMR) technology is an important way to improve the efficiency of modeling and simulation (M&S) and the credibility of simulation results. Recently, following the rapid development of the new technologies (cloud computing, service-oriented architecture (SOA), Web-based simulation, etc.), a mass of tools and architectures on SOMR technologies have been put in use, meanwhile a large number of related papers on SOMR have been published. This paper aims to describe the essence of SOMR briefly through investigating and summarizing the existing researches on SOMR. The contributions of this paper includes: (1) introducing the concepts and evolution process of SOMR;(2) analyzing the motivation and requirements of SOMR;(3) summarizing the general process and the categories of SOMR;and (4) providing a description and comparison of SOMR technologies.

关键词： M&S SOMR Credibility SOA

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Design and FEM simulation of Damped Milling Cutter 16th

引用

Joint conference of the 16th Asia simulation conference / SCS international Autumn simulation Multi-conference (AsiaSim/SCS AutumnSim)

作者： Yang, Yiqing Wang, Yunfei Yu, Yu Beihang Univ Sch Mech Engn & Automat Beijing Peoples R China

ISBN: (纸本)9789811026690;9789811026683

Milling cutter with large length-diameter ratio is usually used in machining complex aerospace parts with deep pockets and thin ribs. Large overhang causes stiffness reduction of the cutting tool, which is a significant factor leading to machining chatter. Damped milling cutter can effectively suppress the vibration. Three structural designs of damped cutter are proposed, and modal analysis and harmonious analysis are performed by ANSYS. simulation results show that the milling cutter embedded with two degree-of-freedom passive damper exhibits the best vibration suppression and the magnitude of frequency response is reduced by 63.7 %, which therefore enhances the machining stability.

关键词： Finite element simulation (FEM) Milling Cutter Passive damper

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Racetrack memory-based encoder/decoder for low-power interconnect architectures

Racetrack memory-based encoder/decoder for low-power interco...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Suman Deb Leibin Ni Hao Yu Anupam Chattopadhyay School of Computer Science and Engineering Nanyang Technological University Singapore School of Electrical and Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781509030774

Spin-based memory devices offer multiple benefits, like, zero standby power, fast operation speed and high write endurance. Besides for storage applications, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic operations, especially in the context of in-memory computing and neuromorphic architectures. In this paper, we propose spin-based design of encoder/decoder which can be used to reduce the power consumption of interconnect architectures in digital systems. Encoding schemes provide a useful way to reduce the power consumption in interconnects and buses. Realizing these schemes require the use of encoders and decoders. Our proposed design can be reconfigured to implement different encoding schemes. Also, the same design can be reconfigured to function either as encoder or as decoder. Our simulations show a 49.65% reduction in dynamic power consumption for 6-bit proposed reconfigurable design when compared with CMOS-only implementation. Compared to the CMOS implementations, the RM-based non-reconfigurable designs show improvements upto 1.8X and 17.34X in leakage and dynamic power respectively.

关键词： Magnetic tunneling Encoding Magnetization computer architecture Integrated circuit interconnections Resistance Power demand

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Aggressively bypassing list scheduler for transport triggered architectures

Aggressively bypassing list scheduler for transport triggere...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Heikki O. Kultala Timo T. Viitanen Pekka O. Jääskeläinen Jarmo H. Takala Department of Pervasive Computing Tampere University of Technology Finland

A new instruction scheduling algorithm for Transport Triggered Architecture (TTA) is introduced. The proposed scheduling algorithm is based on operation-based two-level list scheduling and tries to aggressively bypass data moves before scheduling them and resolves deadlocks by backtracking and bypassing less aggressively those moves that cause deadlocks. Compared to two earlier list schedulers for TTA processors, the proposed scheduler creates code that is on average 2.0 % and 2.2 % and best case of 15.2 % and 16.3 % faster while reducing the amount of register file reads by on average of 9.7 % and 6.9 % and best cases of 31.0 % and 19.0 %, and register file writes on average 18.0 % and 18.9 % and best cases of 48.1 % and 36.8 %. The scheduling time with the proposed scheduler is short enough for the algorithm to be used when performing design space exploration unlike in some instruction schedulers based on mathematical models. The scheduler also introduces a framework, which makes it very easy to be extended to support new optimizations.

关键词： Registers Program processors Processor scheduling Schedules Ports (computers) Scheduling

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Runtime support for adaptive power capping on heterogeneous SoCs

Runtime support for adaptive power capping on heterogeneous ...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Yun Wu Dimitrios S. Nikolopoulos Roger Woods School of Electrical Electronic and Computer Science Queen's University Belfast Belfast United Kingdom

ISBN: (纸本)9781509030774

Power capping is a fundamental method for reducing the energy consumption of a wide range of modern computing environments, ranging from mobile embedded systems to datacentres. Unfortunately, maximising performance and system efficiency under static power caps remains challenging, while maximising performance under dynamic power caps has been largely unexplored. We present an adaptive power capping method that reduces the power consumption and maximizes the performance of heterogeneous SoCs for mobile and server platforms. Our technique combines power capping with coordinated DVFS, data partitioning and core allocations on a heterogeneous SoC with ARM processors and FPGA resources. We design our framework as a run-time system based on OpenMP and OpenCL to utilise the heterogeneous resources. We evaluate it through five data-parallel benchmarks on the Xilinx SoC which allows fully voltage and frequency control. Our experiments show a significant performance boost of 30% under dynamic power caps with concurrent execution on ARM and FPGA, compared to a naive separate approach.

关键词： Kernel Field programmable gate arrays Hardware Servers Resource management Program processors

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A quasi-cycle accurate timing model for binary translation based instruction set simulators

A quasi-cycle accurate timing model for binary translation b...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Sören Schreiner Ralph Görgen Kim Grüttner Wolfgang Nebel OFFIS - Institute for Information Technology Oldenburg Germany Department of Computer Science Carl von Ossietzky Universität Oldenburg Germany

Software defines the functionality of today's Cyber-Physical systems (CPS). Many product innovations are based on software and thus the complexity of software, even when running on platforms equipped with small microprocessors, is increasing dramatically. This calls for adequate embedded software integration testing, even before the actual hardware platform is available. The application of virtual platforms for functional validation, that allows simulating CPS running real target platform application code on a generic host computer, is currently being adopted by the industry. Since the correct behavior of a CPS not only depends on the correctness of computation but also on its timeliness, virtual platforms contain a certain notion of time. This work focuses on enhancing OVP processor models by a quasi-cycle accurate timing model. This paper demonstrates and evaluates the accuracy of the proposed timing model against real hardware measurements for the Xilinx MicroBlaze and ARM Cortex-M0 processors. Results show a mean error of 0.16% for the MicroBlaze and 0.72% for the ARM Cortex-M0 processor over all considered benchmarks, which is a clear improvement compared to previous published work.

关键词： Timing Computational modeling Software Pipelines Hardware Registers Clocks

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MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures

MPSoCSim extension: An OVP simulator for the evaluation of c...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Maria Mendez Real Philipp Wehner Jens Rettkowski Vincent Migliore Vianney Lapotre Diana Göhringer Guy Gogniat Univ. Bretagne-Sud UMR 6285 Lab-STICC Lorient France Ruhr-University Bochum Germany

In this paper, an extension of the OVP based MPSoC simulator MPSoCSim is presented. This latter is an extension of the OVP simulator with a SystemC Network-on-Chip (NoC) allowing the modeling and evaluation of NoC based Multiprocessor systems-on-Chip (MPSoCs). In the proposed version, this extended simulator enables the modeling and evaluation of complex clustered MPSoCs and many-cores. The clusters are compound of several independent subgroups. Each subgroup includes an OVP processor connected by a local bus to its own local memory for code, stack and heap. The subgroups being independent, the attached OVP processor model can be different from the other subgroups (ARM, MicroBlaze, MIPS,...) allowing the simulation of heterogeneous platforms. Also, each processor executes its own code. Subgroups are connected to each other through a shared bus allowing all the subgroups in the cluster to access to a shared memory. Finally, clusters are connected through a SystemC NoC supporting mesh topology with wormhole switching and different routing algorithms. The NoC is scalable and the number of subgroups in each cluster is parameterizable. For a dynamic execution, the OVP processor models support different Operating systems (OS). Also, some mechanisms are available in order to control the dynamic execution of applications on the platform. Different platforms and applications have been evaluated in terms of simulated execution time, simulation time on the host machine and number of simulated instructions.

关键词： Random access memory Compounds Routing Generators Topology Nickel computer architecture

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