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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Exploring system performance using elastic traces: Fast, accurate and portable

Exploring system performance using elastic traces: Fast, acc...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Radhika Jagtap Stephan Diestelhorst Andreas Hansson Matthias Jung Norbert When ARM Research Cambridge United Kingdom Microelectronic Systems Design Research Group University of Kaiserslautern Germany Technische Universitat Kaiserslautern Kaiserslautern Rheinland-Pfalz DE

ISBN: (纸本)9781509030774

simulation tools are indispensable to computer architects. Detailed execution-driven CPU models offer high accuracy, but at the cost of simulation speed. Trace-driven simulation is widely adopted to alleviate this problem, especially for studies focusing on memory-system exploration. Ideally, trace-driven core models will mimic out-of-order processors executing full-system workloads to enable computer architects to evaluate modern systems. Additionally, to be useful to the broader community the tracing and replay models should be publicly available. However, existing trace-driven approaches are limited in their applicability and availability. We propose elastic traces in which we accurately capture data and load/store order dependencies by instrumenting a detailed out-of-order processor model. In contrast to existing work, we do not rely on offline analysis of timestamps, and instead use accurate dependency information tracked inside the processor pipeline. We thereby account for the effects of speculation and branch misprediction resulting in a more accurate trace playback. We provide a trace player that honours the dependencies and thus adapts its execution time to memory-system changes, as would the actual CPU. Compared to the detailed CPU, our trace player achieves a speed-up of 6-8 times. When modifying the memory-system parameters, the average error in absolute execution time is 7% for SPEC 2006 benchmarks on a bare metal system and 17% for HPC benchmarks on Linux. Relative performance is predicted with less than 3% error, achieving fast and accurate system performance exploration. We make this functionality available to the broader community via a widely-used open source full-system simulator.

关键词： Delays Load modeling Computational modeling Out of order Registers Pipelines Generators

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A strong arbiter PUF using resistive RAM

A strong arbiter PUF using resistive RAM

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Swaroop Ghosh Rekha Govindaraj University of South Florida

ISBN: (纸本)9781509030774

Physically Unclonable Functions (PUF) are the cost effective and reliable security primitives widely used in authentication and in-place secret key generation applications. With growing research in the area of non-CMOS technologies for memories and circuits, it's important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration with CMOS due to minimal changes in the process technology. RRAM also demonstrates resistance variability characteristics due to inherent defects in the conducting filament formed inside the metal oxide layer. RRAM based PUF designs exploit either the probabilistic switching of RRAM or the resistance variability during forming, set and reset processes. Memory PUFs using RRAM are weak PUFs with fewer number of Challenge Response Pairs (CRPs). We propose strong arbiter PUF based on 1T-1R bitcell which is obtained from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is employed to generate the response. The PUF is simulated using 65nm predictive technology models for CMOS and verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability and by running NIST benchmarks. The proposed PUF demonstrates mean intra-die Hamming Distance (HD) of mean 0.13% and inter-die HD of mean 51.3%.

关键词： Resistance computer architecture Mathematical model Security Microprocessors Switches Multiplexing

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CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling

CoolSim: Statistical techniques to replace cache warming wit...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Nikos Nikoleris Andreas Sandberg Erik Hagersten Trevor E. Carlson ARM Research Cambridge UK Department of Information Technology Uppsala University Uppsala Sweden

ISBN: (纸本)9781509030774

simulation is an important part of the evaluation of next-generation computing systems. Detailed, cycle-accurate simulation, however, can be very slow when evaluating realistic workloads on modern microarchitectures. Sampled simulation (e.g., SMARTS and SimPoint) improves simulation performance by an order of magnitude or more through the reduction of large workloads into a small but representative sample. Additionally, the execution state just prior to a simulation sample can be stored into checkpoints, allowing for fast restoration and evaluation. Unfortunately, changes in software, architecture or fundamental pieces of the microarchitecture (e.g., hardware-software co-design) require checkpoint regeneration. The end result for co-design degenerates to creating checkpoints for each modification, a task check pointing was designed to eliminate. Therefore, a solution is needed that allows for fast and accurate simulation, without the need for checkpoints. Virtualized fast-forwarding (VFF), an alternative to using checkpoints, allows for execution at near-native speed between simulation points. Warming the micro-architectural state prior to each simulation point, however, requires functional simulation, a costly operation for large caches (e.g., 8 MB). Simulating future systems with caches of many MBs can require warming of billions of instructions, dominating simulation time. This paper proposes CoolSim, an efficient simulation framework that eliminates cache warming. CoolSim uses VFF to advance between simulation points collecting at the same time sparse memory reuse information (MRI). The MRI is collected more than an order of magnitude faster than functional simulation. At the simulation point, detailed simulation with a statistical cache model is used to evaluate the design. The previously acquired MRI is used to estimate whether each memory request hits in the cache. The MRI is an architecturally independent metric and a single profile can be used in simulation

关键词： Magnetic resonance imaging Microarchitecture Software Benchmark testing Computational modeling Data models Electronic mail

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Simulator calibration for accelerator-rich architecture studies

Simulator calibration for accelerator-rich architecture stud...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Mochamad Asri Ardavan Pedram Lizy K. John Andreas Gerstlauer The University of Texas at Austin Austin TX USA Stanford University Stanford CA USA

ISBN: (纸本)9781509030774

Cycle-accurate simulators are widely used in architecture research. A certain degree of performance inaccuracy is expected in such simulators. Such mismatches are tolerable in micro-architectural studies that emphasize relative performance. However, when modeling accelerator-rich heterogeneous systems, an inaccurate baseline CPU model can lead to severe over/underestimation of the speedup and/or energy savings. In this paper, we present a systematic approach and methodology for calibration of cycle-accurate simulators targeting such studies. We further compare the potential impact that an unrepresentative baseline CPU model can have on heterogeneous system design and describe how it could cause to misleading design evaluations. We demonstrate our approach on calibration of MARSSx86, a widely-used, cycle-accurate x86 system simulator. Using our methodology, we calibrate MARSSx86 to closely match the performance of state-of-the-art Intel machines targeting high-performance computing (HPC) benchmarks. Our calibrated MARSSx86 shows on average less than 10% error across a wide range of HPC and general-purpose benchmarks. Using this calibrated baseline simulator, we further quantify the impact of such calibration on an accelerator-rich architecture case study. Our results show that an accelerator estimated to obtain a speedup of 10.3x using unrefined simulators can in reality only achieve a 5.3x speedup when an accurate CPU model is employed.

关键词： Calibration Pipelines Registers computer architecture Computational modeling Acceleration Systematics

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modeling and analysis: Energy harvesting in the internet of things 16

Modeling and analysis: Energy harvesting in the internet of ...

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19th ACM international conference on modeling, Analysis and simulation of Wireless and Mobile systems, MSWiM 2016

作者： Chen, Yu-Hsuan Ng, Bryan Seah, Winston K.G. Pang, Ai-Chun Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan School of Engineering and Computer Science Victoria University of Wellington New Zealand Graduate Institute of Networking and Multimedia National Taiwan University Taipei Taiwan

ISBN: (纸本)9781450345026

In the Internet of Things (IoT), the size constraint of those small and embedded devices limits the network lifetime because limited energy can be stored on these devices. In recent years, energy harvesting technology has attracted increasing attention, due to its ability to extend the network lifetime significantly. However, the performance of IoT devices powered by energy harvesting sources has not been fully analyzed and understood. In this paper, we model the energy harvesting process in IoT devices using slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA /CA) mechanism of IEEE 802.15.4 standard, and analyze the performance in terms of delay and throughput. Our new model successfully integrates the energy harvesting process and binary backoff process through a unified Markov chain model. Finally, the new model is validated by simulation and the throughput errors between simulation and analytical model are no more than 6%. We demonstrate the application of the model with different energy harvesting rate corresponding to different sources such as solar and vibration energy harvesters. © 2016 ACM.

关键词： Internet of things

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TULIPP: Towards ubiquitous low-power image processing platforms

TULIPP: Towards ubiquitous low-power image processing platfo...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Tobias Kalb Lester Kalms Diana Göhringer Carlota Pons Fabien Marty Ananya Muddukrishna Magnus Jahre Per Gunnar Kjeldsberg Boitumelo Ruf Tobias Schuchert Igor Tchouchenkov Carl Ehrenstrahle Magnus Peterson Flemming Christensen Antonio Paolillo Christian Lemer Ben Rodriguez Guillaume Bernard Francois Duhem Philippe Millet Ruhr-University Bochum Germany Efficient Innovation France Norwegian University of Science and Technology Norway Fraunhofer Institute of Optronics System Technologies and Image Exploitation IOSB Germany Synective Labs AB Sweden Sundance Multiprocessor Technology Ltd. UK HIPPEROS S.A. Belgium Thales TED-MIS Thales TRT France Thales TED-MIS Thales TRT France

Many industrial domains rely on vision-based applications which require to comply with severe performance and embedded requirements. Tulipp will develop a reference platform which consists of a hardware system, a tool chain and a real-time operating system. This platform defines implementation rules and interfaces to tackle power consumption issues while delivering high, energy efficient and guaranteed computing performance for image processing applications. Using this reference platform will enable designers to develop a complete solution at a reduced cost to meet the typical embedded systems requirements: Size, Weight and Power. Moreover, for less constrained systems which performance requirements cannot be fulfilled by one instance of the platform, the reference platform will also be scalable so that the resulting boards can be chained for higher processing power. The instance of the reference platform developed during the project will be use-case driven and split between the implementation of: a reference hardware architecture - a scalable low-power board; a low-power operating system and image processing libraries; a productivity-enhancing tool chain. It will lead to three proof-of-concept demonstrators across different application domains: real-time and low-power medical image processing product prototype of surgical X-ray system (mobile c-arm); embedded image processing systems within Unmanned Aerial Vehicles (UAVs); automotive real time embedded systems for driver assistance. Tulipp will set up an ecosystem and will closely work with standardization organizations to propose new standards derived from its reference platform to the industry.

关键词： Image processing Hardware Operating systems Real-time systems Power demand computer architecture Field programmable gate arrays

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AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators

AccuRA: Accurate alignment of short reads on scalable reconf...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Santhi Natarajan N Krishna Kumar Debnath Pal S. K. Nandy Centre for Nano Science and Engineering Indian Institute of Science Bangalore India Indian Institute of Science Bangalore Karnataka IN Department of Computational and Data Sciences Indian Institute of Science Bangalore India

ISBN: (纸本)9781509030774

Classified as a big data problem, Short Read Mapping (SRM) within the Next Generation Sequencing (NGS) pipeline presents profound technical and computing challenges. Existing solutions handle the high volume of data leveraging heuristics, to claim notable performance standards. The results from SRM leave a huge impact across fields, including medical diagnostics and drug discovery. In this context, we need precise, affordable, reliable and actionable results from SRM, to support any application, with uncompromised accuracy and performance. Here, we present AccuRA, a massively parallel, scalable, high performance reconfigurable accelerator for accurate alignment of short reads. Supplemented with multithreaded firmware architecture, AccuRA precisely aligns short reads, at a fine-grained single nucleotide resolution, and offers full coverage of the genome. AccuRA's parallel dynamic programming kernels seamlessly perform traceback process in hardware simultaneously along with forward scan, thus achieving SRM in the minimum possible and deterministic time. The AccuRA prototype, hosting eight kernel units on a single reconfigurable device, aligns short reads with an alignment performance of 20.48 Giga Cell Updates Per Second (GCUPs). AccuRA also scales well at multiple levels of design granularity, while successfully aligning genomes of various sizes, ranging from small archeal, bacterial, fungal genomes, to the large mammalian human genome.

关键词： Genomics Bioinformatics Hardware Heuristic algorithms computer architecture Pipelines Indexes

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A distributed HW-SW platform for fireworks 48

A distributed HW-SW platform for fireworks

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48th Summer computer simulation conference, SCSC 2016, Part of the 2016 Summer simulation Multi-conference, SummerSim 2016

作者： Alonso, Jesus Martin Del Barrio, Alberto A. Universidad Complutense de Madrid Ciudad Universitaria Madrid28040 Spain

ISBN: (纸本)9781510824256

With the scaling of technology, many systems have been able to integrate microcontrollers to improve their functionalities. An example of this integration can be found in the fireworks scenario. Traditionally, fireworks have been directly managed by experts. However, the up-To-date firing systems can be handled remotely. Nevertheless, current solutions are expensive. In this paper we propose a cheap distributed platform able to fire and test a ti reworks show. In order to achieve this, we have designed, simulated and tested a 24 e-matches control node. This node is based on the ESP8266 chip, which possesses WiFi capability, and a transistors matrix that allows managing r∗q outputs with just r+q transistors. simulations and real tests demonstrate the correct behavior of our system, which is cheaper than the state-of-The-Art approaches. © 2016 Society for modeling & simulation international (SCS).

关键词： embedded systems

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2016 international Multidisciplinary conference on computer and Energy Science, SpliTech 2016

2016 International Multidisciplinary Conference on Computer ...

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1st international Multidisciplinary conference on computer and Energy Science, SpliTech 2016

ISBN: (纸本)9789532900637

The proceedings contain 33 papers. The topics discussed include: a framework for thermal building parameter identification and simulation;a review of agent-based modeling of electricity markets in future energy eco-systems;a virtual instrument for efficient blind-source separation of nonstationary signals;a web based virtual environment as a connection platform between people and IoT;an embedded access control system for restricted areas in smart buildings;an improved multi-layer thermal model for photovoltaic modules;an IoT-aware AAL system for elderly people;cardiac arrhythmia detection using DCT based compressive sensing and random forest algorithm;health monitoring system for protecting elderly people;integral equation models in some biomedical applications of electromagnetic fields;location-based smartwatch application for people with complex communication needs;and model business process improvement by statistical analysis of the users' conduct in the process.

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NanoStreams: Codesigned microservers for edge analytics in real time

NanoStreams: Codesigned microservers for edge analytics in r...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Giorgis Georgakoudis Charles Gillan Ahmad Hassan Umar I. Minhas Ivor Spence George Tzenakis Hans Vandierendonck Roger Woods Dimitrios S. Nikolopoulos Murali Shyamsundar Paul Barber Matthew Russell Angelos Bilas Stelios Kaloutsakis Heiner Giefers Peter Staar Costas Bekas Neil Horlock Richard Faloon Colin Pattison School of EEECS Queen's University Belfast Belfast UK The Centre for Infection and Immunity School of Medicine Dentistry and Biomedical Sciences Queen's University Belfast Belfast UK Analytics Engines Belfast UK Institute of Computer Science FORTH Heraklion Greece IBM Research Zurich Rüschlikon Switzerland One Cabot Square London UK Neueda Belfast UK

ISBN: (纸本)9781509030774

NanoStreams explores the design, implementation, and system software stack of micro-servers aimed at processing data in-situ and in real time. These micro-servers can serve the emerging Edge computing ecosystem, namely the provisioning of advanced computational, storage, and networking capability near data sources to achieve both low latency event processing and high throughput analytical processing, before considering off-loading some of this processing to high-capacity data centres. Nano Streams explores a scale-out micro-server architecture that can achieve equivalent QoS to that of conventional rack-mounted servers for high-capacity data centres, but with dramatically reduced form factors and power consumption. To this end, Nano Streams introduces novel solutions in programmable & configurable hardware accelerators, as well as the system software stack used to access, share, and program those accelerators. Our Nano Streams micro-server prototype has demonstrated 5.5 x higher energy-efficiency than a standard Xeon Server. simulations of the micro server's memory system extended to leverage hybrid DDR/NVM main memory indicated 5x higher energy-efficiency than a conventional DDR-based system.

关键词： Hardware Field programmable gate arrays computer architecture Servers Real-time systems Prototypes Instruction sets

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