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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2832 条记录，以下是571-580 订阅

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Globally Asynchronous Locally Synchronous simulation of NoCs on Many-Core architectures

Globally Asynchronous Locally Synchronous Simulation of NoCs...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Marcus Eggenberger Manuel Strobel Martin Radetzki Institut für Technische Informatik Universität Stuttgart Stuttgart Germany

We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly differ not only in the number of processing elements but also in the on-chip communication architecture, the memory subsystem, and the computational performance of an individual core. Proven multi-core simulation approaches do not consider such architectural aspects and thus suffer limited performance when being applied to many-core architectures. To enable high performance simulation, we identify conceptual drawbacks of state of the art parallel simulation approaches and consequently propose a novel globally asynchronous locally synchronous (GALS) simulation concept suited for many-core architectures. Our results show that our GALS simulation approach yields a speedup of up to 2.3 over parallel discrete event simulation.

关键词： computer architecture Synchronization Computational modeling Message systems Data models Discrete event simulation Instruction sets

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Proceedings - 23rd IEEE international conference on High Performance Computing, HiPC 2016

Proceedings - 23rd IEEE International Conference on High Per...

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23rd IEEE international conference on High Performance Computing, HiPC 2016

ISBN: (纸本)9781509054114

The proceedings contain 40 papers. The topics discussed include: fault tolerant frequent pattern mining;parallel performance-energy predictive modeling of browsers: case study of servo;optimization of brain mobile interface applications using IoT;Mizan-RMA: accelerating Mizan graph processing framework with MPI RMA;CUDA M3: designing efficient CUDA managed memory-aware MPI by exploiting GDR and IPC;parallel implementation of lossy data compression for temporal data sets;scalable parallel algorithms for shared nearest neighbor clustering;DCRoute: speeding up inter-datacenter traffic allocation while guaranteeing deadlines;efficient data redistribution to speedup big data analytics in large systems;MEC: the memory elasticity controller;Phoenix: memory speed HPC I/O with NVM;dynamic data layout optimization for high performance parallel I/O;read consistency in distributed database based on DMVCC;data elevator: low-contention data movement in hierarchical storage system;CMT-Bone - A Proxy application for compressible multiphase turbulent flows;tensor contractions with extended BLAS kernels on CPU and GPU;memory-efficient parallel simulation of electron beam dynamics using GPUs;cache-friendly design for complex spatially-variable coefficient stencils on many-core architectures;using message logs and resource use data for cluster failure diagnosis;and PRESAGE: protecting structured address generation against soft errors.

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A Statistical Model for Hybrid Wireless Network on Chip

A Statistical Model for Hybrid Wireless Network on Chip

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international conference on VLSI Design

作者： Priyanka Mitra Department of Computer Science and Engineering Malaviya National Institute of Technology Rajasthan India

A scalable and easy to design solution for the continuing demand of high performance chip multiprocessors paved the way for Hybrid Wireless Network on Chip (WiNoC) architectures which comprises of both wired and wireless channel interconnects for communication. The simulation results of this emerging communication architecture outperforms other traditional interconnects in performance gain for multicore systems. Besides simulation, statistical modelling is another way to measure system performance. This paper proposes a statistical model based on queuing theory to measure performance of scalable Hybrid Wireless Network on Chip (WiNoC) architecture. The statistical model studies the transition state distribution and steady state distribution of flits in the input channel and analyzes average number of flits and average waiting time of flits in the wireless channel. The proposed statistical model predictions have been verified with the simulation results which shows that the relative error between the two results to determine the average latency of the flits and the number of flits lies within 5%. The statistical model also determines the critical value when the network enters into the state of congestion. Thus the proposed statistical model has been verified and validated accurately with the simulation results.

关键词： Queueing analysis Analytical models Wireless networks computer architecture Mathematical model Probability

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MPSoCSim: An extended OVP Simulator for modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs 15

MPSoCSim: An extended OVP Simulator for Modeling and Evaluat...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Wehner, Philipp Rettkowski, Jens Kleinschmidt, Tobias Goehringer, Diana Ruhr Univ Bochum Bochum Germany

ISBN: (纸本)9781467373111

In this paper a SystemC simulator for Network-on-Chip (NoC) based Multiprocessor systems-on-Chip (MPSoCs) is presented. The simulator currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First and an adaptive West-First algorithm. The impact of routing algorithms regarding performance can be analyzed by means of the presented simulator. In order to simulate a heterogeneous MPSoC, ARM processors and MicroBlazes can be attached to the NoC. Processor and peripheral models used within the test platforms are provided by Imperas/OVP. Moreover, traffic generators are available to analyze the system. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator multiple platforms and applications were put under test and compared with a hardware implementation. The comparison shows that the simulator improves the development of MPSoCs by early estimation of system requirements.

关键词： MPSoC simulator Network-on-Chip heterogeneous MPSoC routing algorithms OVP

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A Lightweight Infrastructure for the Dynamic Creation and Configuration of Virtual Platforms 15

A Lightweight Infrastructure for the Dynamic Creation and Co...

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international conference on embedded computer systems architectures modeling and simulation

作者： Sauer, Christian Loeb, Hans-Peter Cadence Design Syst Munich Germany

ISBN: (纸本)9781467373111

Virtual prototypes leverage SystemC/TLM for simulating programmable platforms comprising 100s of modules. Their efficient creation and configuration is vital for acceptable turnaround times, e.g., during performance exploration or software development. Therefore, our lightweight infrastructure provides a factory creating designs from abstract descriptions of module instances, properties, and connections. Modules mark properties as creation or runtime parameters. The resulting generic design descriptions are usable by non-experts and enable front-ends. The infrastructure is a small C++ library that can be combined with existing SystemC/TLM models and simulation kernels. An industrial case study of a complex multiprocessor SoC shows a distinct productivity gain.

关键词： INFRASTRUCTURE Lightweight configurations creation Platform Virtual Software design computer software simulating

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Platform-aware Dynamic Data Type Refinement Methodology for Radix Tree Data Structures 15

Platform-aware Dynamic Data Type Refinement Methodology for ...

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international conference on embedded computer systems architectures modeling and simulation

作者： Papastergiou, Thomas Papadopoulos, Lazaros Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece

ISBN: (纸本)9781467373111

Modern embedded systems are now capable of executing complex and demanding applications that are often based on large data structures. The design of the critical data structures of the application affects the performance and the memory requirements of the whole system. Dynamic Data Structure Refinement methodology provides optimizations, mainly in list and array data structures, which are based on the application's features and access patterns. In this work, we extend various aspects of the methodology: First, we integrate radix tree optimizations. Then, we provide a set of platform-aware data structure implementations, for performing optimizations based on the hardware features. The extended methodology is evaluated using a wide set of synthetic and real-world benchmarks, in which we achieved performance and memory trade-offs up to 29.6%. Additionally, Pareto optimal data structure implementations that were not available by the previous methodology, are identified with the extended one.

关键词： Data structures memory requirements Root Radix Base of a number system tree data structures embedded systems data types Refining Not Available computer hardware

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Towards the design of fault-tolerant mixed-criticality systems on multicores

Towards the design of fault-tolerant mixed-criticality syste...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Luyuan Zeng Pengcheng Huang Lothar Thiele Computer Engineering Group (TEC) ETH Zurich

ISBN: (纸本)9781509035892

Mixed-criticality is a significant recent trend in the embedded system industry, where common computing platforms are utilized to host functionalities of varying criticality levels. To date, most scheduling techniques have focused on the timing aspect of this problem, while functional safety (i.e. fault-tolerance) is often neglected. This paper presents design methodologies to guarantee both safety and schedulability for real-time mixed-criticality systems on identical multicores. Assuming hardware/software transient errors, we model safety requirements on different criticality levels explicitly according to safety standards; based on this, we further propose fault-tolerant mixed-criticality scheduling techniques with task replication and re-execution to enhance system safety. To cope with runtime urgencies where critical tasks do not succeed after a certain number of trials, our techniques can perform system reconfigurations (task killing or service degradation) in those situations to reallocate system resources to the critical tasks. Due to explicit modeling of safety, we can quantify the impact of task killing and service degradation on system feasibility (safety and schedulability), enabling a rigorous design. To this end, we derive analysis techniques when reconfigurations are triggered either globally (synchronously) on all cores or locally (asynchronously) on each core. To our best knowledge, this is the first work on fault-tolerant mixed-criticality scheduling on multicores, matching theoretical insights with industrial safety standards. Our proposed techniques are validated with an industrial application and extensive simulations.

关键词： Safety Multicore processing Fault tolerant systems Standards Redundancy Runtime

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Multi-Domain SystemC Model of 128-Channel Time-Multiplexed Neural Interface Front-End 15

Multi-Domain SystemC Model of 128-Channel Time-Multiplexed N...

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international conference on embedded computer systems architectures modeling and simulation

作者： Wirianto, Kiki Zjajo, Amir Galuzzi, Carlo van Leuken, Rene Delft Univ Technol Circuits & Syst Grp Delft Netherlands Maastricht Univ BMI Res Grp Maastricht Netherlands

ISBN: (纸本)9781467373111

A SystemC Multi-Domain Virtual Prototype (MDVP) framework provides multi-domain system integration of multi-electrode neural interface and a fast validation time, offering more efficient design process. In this paper, we propose efficient neuron cell, neuron tissue, and multi-channel neural interface front-end models implemented in a SystemC MDVP framework, which supports chemical, biological, and electrical domain modeling and simulation. The proposed model offers advantages for designers not only in reducing the design time, but also regarding the system integration. We make use of 8x16-channel front-end recording circuits to implement a 128-channel time-multiplexed neural interface front-end model. These models are verified with realistic simulation settings and appropriate input signals.

关键词： SystemC MDVP modeling multi-channel front-end neural interface

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HEVC In-Loop Filters GPU Parallelization in embedded systems 15

HEVC In-Loop Filters GPU Parallelization in Embedded Systems

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international conference on embedded computer systems architectures modeling and simulation

作者： de Souza, Diego F. Ilic, Aleksandar Roma, Nuno Sousa, Leonel Univ Lisbon IST INESC ID Rua Alves Redol 9 P-1000029 Lisbon Portugal

ISBN: (纸本)9781467373111

The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied devices. To circumvent this limitation, this paper proposes the exploitation of embedded GPU devices already equipping many state of the art SoCs to accelerate the HEVC in-loop filters (i.e. deblocking filter and sample adaptive offset). The presented approaches comprehensively exploit both fine and coarse-grained parallelization opportunities of these filters in an NVIDIA Tegra GPU. According to the conducted experimental evaluation, the proposed approach showed to be a remarkable strategy to satisfy the real-time requirements of the HEVC decoder, being able to filter each Ultra HD 4K intra frame in less than 20 ms (about 50 fps).

关键词： Filters embedded systems High efficiency video coding parallelization GRAPPER PICK UP Graphics Processing Unit ENCODER decoders state of the art complexity classes

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Parallelism Extraction in embedded Software for Android Devices 15

Parallelism Extraction in Embedded Software for Android Devi...

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international conference on embedded computer systems architectures modeling and simulation

作者： Aguilar, Miguel Angel Eusse, Juan Fernando Ray, Projjol Leupers, Rainer Ascheid, Gerd Sheng, Weihua Sharma, Prashant Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany Samsung R&D Inst Surrey England

ISBN: (纸本)9781467373111

In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor systems on Chip (MPSoCs) is a widely accepted solution to provide a trade-off between these demands. However, programming MPSoCs is still a cumbersome task. Several research efforts have addressed this challenge in two complementary directions: paradigms for parallel programming and tools for parallelism extraction. However, most of these efforts are focused on the high performance domain and they do not consider the characteristics of the underlying platform. In this paper, we present an approach to extract multiple forms of parallelism from sequential C code, which is applied to widespread Android mobile devices. We show the effectiveness of our work by parallelizing relevant embedded benchmarks on a quad-core Nexus 7 tablet.

关键词： Androids embedded software parallelism Synclitism Methyltestosterone embedded device Multiple forms Parallel programming everyday life C CODES

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