Mixed-criticality is a significant recent trend in the embedded system industry, where common computing platforms are utilized to host functionalities of varying criticality levels. To date, most scheduling techniques...
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ISBN:
(纸本)9781509035892
Mixed-criticality is a significant recent trend in the embedded system industry, where common computing platforms are utilized to host functionalities of varying criticality levels. To date, most scheduling techniques have focused on the timing aspect of this problem, while functional safety (i.e. fault-tolerance) is often neglected. This paper presents design methodologies to guarantee both safety and schedulability for real-time mixed-criticality systems on identical multicores. Assuming hardware/software transient errors, we model safety requirements on different criticality levels explicitly according to safety standards; based on this, we further propose fault-tolerant mixed-criticality scheduling techniques with task replication and re-execution to enhance system safety. To cope with runtime urgencies where critical tasks do not succeed after a certain number of trials, our techniques can perform system reconfigurations (task killing or service degradation) in those situations to reallocate system resources to the critical tasks. Due to explicit modeling of safety, we can quantify the impact of task killing and service degradation on system feasibility (safety and schedulability), enabling a rigorous design. To this end, we derive analysis techniques when reconfigurations are triggered either globally (synchronously) on all cores or locally (asynchronously) on each core. To our best knowledge, this is the first work on fault-tolerant mixed-criticality scheduling on multicores, matching theoretical insights with industrial safety standards. Our proposed techniques are validated with an industrial application and extensive simulations.
A SystemC Multi-Domain Virtual Prototype (MDVP) framework provides multi-domain system integration of multi-electrode neural interface and a fast validation time, offering more efficient design process. In this paper,...
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ISBN:
(纸本)9781467373111
A SystemC Multi-Domain Virtual Prototype (MDVP) framework provides multi-domain system integration of multi-electrode neural interface and a fast validation time, offering more efficient design process. In this paper, we propose efficient neuron cell, neuron tissue, and multi-channel neural interface front-end models implemented in a SystemC MDVP framework, which supports chemical, biological, and electrical domain modeling and simulation. The proposed model offers advantages for designers not only in reducing the design time, but also regarding the system integration. We make use of 8x16-channel front-end recording circuits to implement a 128-channel time-multiplexed neural interface front-end model. These models are verified with realistic simulation settings and appropriate input signals.
The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. Ho...
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ISBN:
(纸本)9781467373111
The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embeddedsystems, mobile and battery supplied devices. To circumvent this limitation, this paper proposes the exploitation of embedded GPU devices already equipping many state of the art SoCs to accelerate the HEVC in-loop filters (i.e. deblocking filter and sample adaptive offset). The presented approaches comprehensively exploit both fine and coarse-grained parallelization opportunities of these filters in an NVIDIA Tegra GPU. According to the conducted experimental evaluation, the proposed approach showed to be a remarkable strategy to satisfy the real-time requirements of the HEVC decoder, being able to filter each Ultra HD 4K intra frame in less than 20 ms (about 50 fps).
In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor...
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ISBN:
(纸本)9781467373111
In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor systems on Chip (MPSoCs) is a widely accepted solution to provide a trade-off between these demands. However, programming MPSoCs is still a cumbersome task. Several research efforts have addressed this challenge in two complementary directions: paradigms for parallel programming and tools for parallelism extraction. However, most of these efforts are focused on the high performance domain and they do not consider the characteristics of the underlying platform. In this paper, we present an approach to extract multiple forms of parallelism from sequential C code, which is applied to widespread Android mobile devices. We show the effectiveness of our work by parallelizing relevant embedded benchmarks on a quad-core Nexus 7 tablet.
With the embedded system showing a trend of network development, and gradually formed a Cyber-physical systems. How to ensure the safety and reliability of the Cyber-physical systems is a hot research topic in the pre...
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ISBN:
(纸本)9781509037148
With the embedded system showing a trend of network development, and gradually formed a Cyber-physical systems. How to ensure the safety and reliability of the Cyber-physical systems is a hot research topic in the present study. Full-digital co-simulation technology is an important means of verify the safety and reliability of embedded system, Cooperative communication is one of the key models of full-digital co-simulation system. Its network structure may affect simulation results and performance of system directly. Peer-to-Peer (P2P) network, a networking pattern developed rapidly in recent years, boasts unique advantages in coordinated working, P2P computing, resource sharing, etc. The paper studies the architecture of P2P network, proposes a P2P-based full digital co-simulation and verification system, focuses on the issuance/subscription mechanism of software bus, recommended strategy for timing simulation and activity detection mechanism of simulation node in the system, and designs experiments for analyzing the real-time simulation of the system.
This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained s...
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ISBN:
(纸本)9781467373111
This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained streaming applications and multiple latency-constrained feedback control applications onto a multi-processor platform running under a Time-Division Multiple-Access (TDMA) policy. The main objective of the proposed method is to reduce resource usage while meeting constraints from both these two domains (i.e., throughput and latency constraints). We show by experiments that the overall resource usage for this mapping problem can be reduced by distributing the allocated resource (i.e., TDMA slots) to the control applications over the TDMA wheel instead of allocating consecutive slots.
Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This pre...
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ISBN:
(纸本)9781467373111
Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The evaluation for the ARM Cortex-A9 processor shows that the proposed approach is able to achieve a high accuracy. In comparison to hardware power measurements obtained from the OMAP4460 chip on the PandaBoard, the ESL estimation error is below 5%.
Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi-and many-processor systems-on-chip (MPSoCs). VPs provide unrivalled controllability and visibility of the target, which can be e...
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ISBN:
(纸本)9781467373111
Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi-and many-processor systems-on-chip (MPSoCs). VPs provide unrivalled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware. However, VPs as used for debugging provide only traditional interfaces, such as step-based debuggers and traces, that do little to help with the enormous complexity of MPSoCs and their parallel software. Finding a bug is still largely left to the developer's experience and intuition, using manual means rather than automated solutions. To bridge this gap, this paper presents a novel VP debug visualization and control framework for concurrent software that allows examining and steering the target by means of an abstract representation of its inter-task interactions. Our framework reduces the effort required to understand complex concurrency patterns and helps to expose bugs.
Safety verification of embeddedsystems modeled as hybrid systems can be scaled up by employing simulation-guided reach set over-approximation techniques. Existing methods are either applicable to only restricted clas...
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ISBN:
(纸本)9781509035915
Safety verification of embeddedsystems modeled as hybrid systems can be scaled up by employing simulation-guided reach set over-approximation techniques. Existing methods are either applicable to only restricted classes of systems, overly conservative, or computationally expensive. We present new techniques to compute a locally optimal bloating factor based on discrepancy functions, which allow construction of reach set over-approximations from simulation traces for general nonlinear systems. The discrepancy functions are critical for tools like C2E2 to verify bounded time safety properties for complex hybrid systems with nonlinear continuous dynamics. The new discrepancy function is computed using local bounds on a matrix measure under an optimal metric such that the exponential change rate of the discrepancy function is minimized. The new technique is less time consuming and less conservative than existing techniques and does not incur significant computational overhead. We demonstrate the effectiveness of our approach by comparing the performance of a prototype implementation with the state-of-the-art reachability analysis tool Flow*.
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power c...
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Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.
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