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international conference on embedded computer systems architectures modeling and simulation

作者： Rodopoulos, Dimitrios Corbetta, Simone Massari, Giuseppe Libutti, Simone Catthoor, Francky Sazeides, Yiannakis Nicopoulos, Chrysostomos Portero, Antoni Cappe, Etienne Vavrik, Radim Vondrak, Vit Soudris, Dimitrios Sassi, Federico Fritsch, Agnes Fornaciari, William NTUA ECE ICCS MicroLab Athens Greece SSET Imec Leuven Belgium Katholieke Univ Leuven ESAT Leuven Belgium UCY multiCAL Nicosia Cyprus DEIB POLIMI Milan Italy IT4Innovations VSB TUO Poruba Czech Republic Thales Grp La Defense France Henesis Srl Parma Pr Italy

ISBN: (纸本)9781467373111

Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need to be carefully considered so that the dependability of digital systems can be guaranteed. Already, architectures contain many mechanisms that detect and correct physically induced reliability violations. In many cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper discusses the FP7-612069-HARPA project of the European Commission and its approach towards dependable performance. This project provides solutions for performance variability mitigation, under the run time presence of fabric variability/aging and built-in reliability, availability and serviceability (RAS) techniques. In this paper, we briefly present and discuss modeling and mitigation techniques developed within HARPA, covering many abstractions of digital system design: from the transistor to the application layer.

关键词： Degradation Dynamic Voltage and Frequency Scaling embedded Computing High Performance Computing Performance Vulnerability Factor Resource Management Variability

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Synchronization Considerations for Real-Time Wireless Sensor and Actuator Networks

Synchronization Considerations for Real-Time Wireless Sensor...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Deji Chen Mark Nixon Shaobo Zheng Tao Gong Song Han Aloysius K. Mok Ministry of Education Tongji University Shanghai China Emerson Process Management Round Rock TX USA Department of Computer Science and Engineering University of Connecticut Storrs CT USA Department of Computer Science University of Texas Austin TX USA

ISBN: (纸本)9781509024803

Wireless sensing and networking technologies have taken a strong foothold in the process control industry. The focus has now shifted towards applying control with wireless technology. As such, the current industrial wireless sensor network architectures are under increased scrutiny about their real-time, reliability, and security performances. In this paper, we take a renewed look at network synchronization, the basic building block to support real-time activities. We present our analysis, key observations, and recommendations. We also get into the depth of WirelessHART, the most deployed industrial wireless network architecture, and affirm that, with good practice, we could achieve highly reliable synchronization to provide guaranteed packet deliveries. The correctness of the time synchronization analysis in both line and mesh network topologies is verified through extensive simulation experiments.

关键词： Synchronization Clocks Wireless sensor networks Peer-to-peer computing Wireless communication Communication system security Real-time systems

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Validation of a predictive model for smart control of electrical energy storage

Validation of a predictive model for smart control of electr...

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IEEE international Energy conference and Exhibition (EnergyCon)

作者： Bart Homan Gerard J.M. Smit Richard P. van Leeuwen Lei Zhu Jan B. de Wit Computer Architectures and Embedded Systems University of Twente Enschede The Netherlands Saxion University of Applied Sciences Enschede The Netherlands

ISBN: (纸本)9781467384643

The purpose of this paper is to investigate the applicability of a relatively simple model which is based on energy conservation for model predictions as part of smart control of thermal and electric storage. The paper reviews commonly used predictive models. Model predictions of charging and discharging cycles are compared with experimental data of a domestic hot water thermal storage and lead acid batteries.

关键词： Batteries State of charge Mathematical model Discharges (electric) Predictive models Computational modeling

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SOC Design for Wireless Communications

SOC Design for Wireless Communications

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international conference on VLSI Design

作者： Zoran Stamenkovic IHP Frankfurt (Oder) Germany

Summary form only given. A common denominator of system-on-chip (SOC) design is research of how to integrate a whole system on one silicon chip. The tutorial emphasizes design methods, architectures and circuits towards system level integration. It gives the basic knowledge and skills for designing small, low-power, embedded devices. Besides tackling issues of functionality, an important goal is to understand the balancing of production cost, development time, and performance of such devices. The complexity of these devices increases exponentially, and so does the effort of designing such systems. Only by using an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The tutorial bundles these topics in order to provide a good understanding of all problems involved. Finally, it teaches how to design large systems and shows how to go from description and simulation to implementation and testing. A good SOC design flow assumes getting a design from the architectural level or RTL level to the chip layout. It should provide the designer with a working starting point for each stage of the design process. The tutorial describes such a methodology that relies on a library of configurable IP cores and custom hardware accelerators and satisfies the unique needs of wireless applications. The SOC design flow will be thoroughly examined with examples drawn from wireless communications.

关键词： Tutorials System-on-chip Wireless communication Design methodology Complexity theory Hardware Integrated circuit modeling

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modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators

Modeling a switch architecture with virtual output queues an...

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international conference on High Performance Computing & simulation (HPCS)

作者： Pedro Yébenes German Maglione-Mathey Jesus Escudero-Sahuquillo Pedro J. García Francisco J. Quiles Dept. of Computing Sytems University of Castilla-La Mancha Spain

The high-performance switches used in the interconnection networks of HPC systems have evolved in the last years incorporating new features that were proposed decades ago as theoretical concepts but were then unfeasible due to technological constraints. One of these features are the Virtual Output Queues (VOQs) which can be included in current switch architectures. This approach consists in implementing at each input port as many queues as there are output ports in order to eliminate low-order Head-of-Line blocking. Besides VOQs, Virtual Channels (VCs) are usually implemented in current switch architectures. Both features can be jointly configured to improve switch performance. For that reason, new techniques and proposals exploit their advantages while they solve their drawbacks. Usually, the earliest evaluations of these new improvements are performed using network simulators. These tools allow network designers and manufactures to save time in the testing and development of new components. This paper focuses on the modeling of a switch architecture with VOQs and VCs and its implementation in HPC-systems simulators. We describe the basics of the pipelined switch architecture assumed for the model, i.e., the stages and operations applied to packets crossing it. We also detail the modeling of VOQs through several pseudo-code algorithms, ready to be adapted to any network simulator. Finally, we use an OMNeT++-based simulator for implementing and evaluating the model by means of several topologies, traffic scenarios and buffer organizations.

关键词： Switches Ports (computers) computer architecture Adaptation models Buffer storage Computational modeling

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GPU Implementation of an Anisotropic Huber-L¹ Dense Optical Flow Algorithm Using OpenCL 15

GPU Implementation of an Anisotropic Huber-<i>L</i><SUP>1</S...

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international conference on embedded computer systems architectures modeling and simulation

作者： Buyukaydin, Duygu Akgun, Toygar ASELSAN Transportat Secur Energy & Automat Syst UGES Busi Ankara Turkey

ISBN: (纸本)9781467373111

Optical flow estimation aims at inferring a dense pixel-wise correspondence field between two images or video frames. It is commonly used in video processing and computer vision applications, including motion-compensated frame processing, extracting temporal features, computing stereo disparity, understanding scene context/dynamics and understanding behavior. Dense optical flow estimation is a computationally complex problem. Fortunately, a wide range of optical flow estimation algorithms are embarrassingly parallel and can efficiently be accelerated on GPUs. In this work we discuss a massively multi-threaded GPU implementation of the anisotropic Huber-L-1 optical flow estimation algorithm using OpenCL framework, which achieves per frame execution time speed-up factors up to almost 300x. Overall algorithm flow, GPU specific implementation details and performance results are presented.

关键词： Optic Flow Traffic estimation GRAPPER PICK UP Graphics Processing Unit Understanding behavior images Dense Videotapes Frame Anisotropy computer vision

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Learning-based Analytical Cross-Platform Performance Prediction 15

Learning-based Analytical Cross-Platform Performance Predict...

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international conference on embedded computer systems architectures modeling and simulation

作者： Zheng, Xinnian Ravikumar, Pradeep John, Lizy K. Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781467373111

As modern processors are becoming increasingly complex, fast and accurate performance prediction is crucial during the early phases of hardware and software co-development. To accurately and efficiently predict the performance of a given software workload is, however, a challenging problem. Traditional cycle-accurate simulation is often too slow, while analytical models are not sufficiently accurate or still require target-specific execution statistics that may be slow or difficult to obtain. In this paper, we propose a novel learning-based approach for synthesizing analytical models that can accurately predict the performance of a workload on a target platform from various performance statistics obtained directly on a host platform using built-in hardware counters. Our learning approach relies on a one-time training phase using a cycle-accurate reference of the chosen target processor. We train our models on over 15,000 program instances from the ACM-ICPC programming contest database, and demonstrate the prediction accuracy on standard benchmark suites. Result show that our approach achieves on average more than 90% accuracy at 160x the speed compared to a cycle-accurate reference simulation.

关键词： performance prediction ANALYSIS MODELS Workload standardized benchmark computer hardware PROCESSOR

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Framework for Parameter Analysis of FPGA-based Image Processing architectures 15

Framework for Parameter Analysis of FPGA-based Image Process...

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international conference on embedded computer systems architectures modeling and simulation

作者： Reichenbach, Marc Pfundt, Benjamin Fey, Dietmar Univ Erlangen Nurnberg Comp Architecture Martensstr 3 D-91058 Erlangen Germany

ISBN: (纸本)9781467373111

Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the description of stencil codes. A promising approach in embedded systems is to use the massively parallel computation power of an FPGA for this kind of algorithms. This not only speeds up processing time, if the FPGA is directly placed inside the image acquisition unit forming a smart camera, but also reduces or even eliminates the PC based hardware which saves space and power. However, most designers begin from scratch when they have to implement stencil computations into smart cameras. This leads to a not fully utilized FPGA because the most efficient usage of the given resources is only secondary alongside functional correctness. Therefore, we are presenting in this paper a framework for stencil code applications which immediately delivers the best architecture regarding prominent resource criteria. An analytical model is used to find an optimized parameter set (degree of parallelism, usage of buffers, etc.) for a highly flexible FPGA implementation. A graphical tool allows to further evaluate the effects of certain parameters. Our results show, that we are able to create an optimized hardware architecture for this application domain.

关键词： stencil computation parallel processing analytical model optimization full buffering

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Guest Editorial: Special Issue on embedded computer systems: architectures, modeling and simulation

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international JOURNAL OF PARALLEL PROGRAMMING 2015年第1期43卷 1-2页

作者： McAllister, John Guevorkian, David Jeschke, Hartwig Sima, Mihai Queens Univ Belfast Belfast Antrim North Ireland Tampere Univ Technol FIN-33101 Tampere Finland Leibniz Univ Hannover D-30167 Hannover Germany Univ Victoria Victoria BC Canada

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Cognitive robot programming using procedural parameters and complex event processing

Cognitive robot programming using procedural parameters and ...

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IEEE international conference on simulation, modeling, and Programming for Autonomous Robots (SIMPAR)

作者： Floris Erich Kenji Suzuki Tsukuba Daigaku Tsukuba Ibaraki JP Faculty of Engineering Information and Systems University of Tsukuba

ISBN: (纸本)9781509046171

Current robot software architectures use the publish/subscribe messaging protocol to enable communication between components. The messages published by a component have to meet the specifications of components subscribing to these messages. Because of this, components can often not be used directly together and either have to be modified first or need to be wrapped using connector components. This increases the amount of work required to develop robot software. In this paper we propose Complex Events Processing (CEP) with Procedural Parameters as an alternative solution. CEP allows a developer to use various operators besides subscribe to define the communication between components. These operators for example allow mapping, filtering and sampling of messages. To be able to provide a generic set of operators which can be used in any robot application, we allow developers to define procedures as parameters to the operators. The procedures act as a strategy for the computation to be performed, the operator defining what should be done and the procedural parameter defining how to do it. Through an example we show that CEP can be used for creating robot behaviors.

关键词： Robot sensing systems Programming Observers Actuators computer architecture Time division multiplexing

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