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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Current Analysis Approaches and Performance Needs for Whole Slide Image Processing in Breast Cancer Diagnostics 15

Current Analysis Approaches and Performance Needs for Whole ...

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international conference on embedded computer systems architectures modeling and simulation

作者： Pollanen, Irene Braithwaite, Billy Haataja, Keijo Ikonen, Tiia Toivanen, Pekka Univ Eastern Finland Sch Comp Kuopio Campus Kuopio Finland

ISBN: (纸本)9781467373111

In this paper, the current approaches and performance needs for whole slide image (WSI) analysis processing in breast cancer diagnostics are discussed. WSIs provide high resolution digital image data from the patient's diseased tissue. Digital whole slide images are typically very large and contain a high amount of information. Digitizing tissue specimen into the form of digital images allows the development and application of computational analysis algorithms. Biological tissues are complex with variance in tissue structures between healthy individuals as well as between patients with the same disease. Furthermore, the tissue preparation and digitization usually generates a lot of artifacts and more complexity, which causes classification challenges. This variance and also the large size of the images make creating an accurate and reliable automated breast cancer image analysis a challenge. In the ALMARVI project we aim at generating and implementing efficient histopathological image analysis algorithms in our breast cancer analysis scheme. This paper focuses on discussing relevant information concerning histopathological breast cancer diagnosis, and could also be considered as an introduction to the concept of WSI analysis to non-experts. Since the WSI sizes are very large (up to 40 GB with no compression) there are challenges on the computational analysis which requires computationally efficient tools and suitable approaches to relieve the problems caused by the large size of the images.

关键词： whole slide image breast cancer computer-aided diagnosis

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Reconfigurable computing for future vision-capable devices 15

Reconfigurable computing for future vision-capable devices

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15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： López, Miguel Bordallo Nieto, Alejandro Silvén, Olli Bóutellier, Jani Vilariño, David López University of Oulu Finland CITIUS Universidad de Santiago de Compostela Spain

ISBN: (纸本)9781467373111

Mobile devices have been identified as promising platforms for interactive vision-based applications. However, this type of applications still pose significant challenges in terms of latency, throughput and energy-efficiency. In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant performance benefits compared to general purpose architectures. This paper presents concepts laying on platform level adaptability, exploring the acceleration of vision-based interactive applications through the utilization of three reconfigurable architectures: A low-power EnCore processor with a Configurable Flow Accelerator co-processor, a hybrid reconfigurable SIMD/MIMD platform and Transport-Triggered Architecture-based processors. The architectures are evaluated and compared with current processors, analyzing their advantages and weaknesses in terms of performance and energy-efficiency when implementing highly interactive vision-based applications. The results show that the inclusion of reconfigurable platforms on mobile devices can enable the computation of several computationally heavy tasks with high performance and small energy consumption while providing enough flexibility. © 2015 IEEE.

关键词： Reconfigurable architectures

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A novel framework for optimal component based data center architecture

A novel framework for optimal component based data center ar...

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international conference on Information Communication and embedded systems (ICICES)

作者： Kunja Nagamani Ch. G. V. N. Prasad K. Shahu Chatrapati Department of Computer science and Engineering Sai Spurthi Institute of Technology Sathupally Telangana INDIA Department of Computer science and Engineering Sri Indu College of Engineering and Technology Hyderabad TELANGANA INDIA Department of Computer science and Engineering Jawaharlal Nehru Technological University Hyderabad TELANGANA INDIA

ISBN: (纸本)9781509025534

With the tremendous growth of applications and wide demand of high performance architecture, the demand for virtual or cloud based architecture is also growing. The architecture demand focused on computing, storage and networking is directing the research towards the cloud based data centers. The migration towards the cloud based data centers from the traditional data centers is the recent trends of the modernization of architecture to match the demand of high performance computing. However the optimal settings of hardware availability based on the utilization, up time and cost factors is yet to be determined. Also the generic performance and setup differences between traditional data centers and cloud based data centers are also to be defined. The recent progress of the researches limit to justify the complexities of cloud based data center architecture. Moreover the most suitable performance matrix to evaluate the data center hardware performance is also to be defined. Thus this work demonstrates the framework for optimal component based data center architecture reducing the redundant components and evaluates the performance of the framework on the proposed matrix for data center hardware component evaluation. Moreover this work demonstrates the fundamental strategies of data center hardware resource optimization. The final outcome of this work is optimal framework simulation tool based on CloudSim toolkit.

关键词： Cloud computing Smart grids computer architecture Hardware Optimization Computational modeling High performance computing

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3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems 15

3D-Stacked Many-Core Architecture for Biological Sequence An...

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international conference on embedded computer systems architectures modeling and simulation

作者： Liu, Pei Hemani, Ahmed Paul, Kolin KTH Royal Inst Technol Dept Elect Syst Sch ICT Stockholm Sweden Indian Inst Technol Dept Comp Sci & Engn New Delhi India

ISBN: (纸本)9781467373111

Sequence analysis plays critical role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70% of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array (CGRA) we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of 68 mm2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than any existed hardware accelerators for at least 39 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.

关键词： Accelerator architectures Application specific integrated circuits Bioinformatics Computational biology Coprocessors Reconfigurable architectures Three-dimensional integrated circuits

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Proceedings - 2009 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2009

Proceedings - 2009 International Conference on Embedded Comp...

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2009 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2009

ISBN: (纸本)9781424445011

The proceedings contain 23 papers. The topics discussed include: a mixed hardware-software approach to flexible artificial neural network training on FPGA;high-speed FPGA-based implementations of a genetic algorithm;high-level synthesis for the design of FPGA-based signal processing systems;a physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors;instruction-based reuse-distance prediction for effective cache management;adaptive simulation sampling using an autoregressive framework;an emulation-based real-time power profiling unit for embedded software;generation and calibration of compositional performance analysis models for multi-processor systems;performance evaluation of concurrently executing parallel applications on multi-processor systems;and multi-processor system-on-chip design space exploration based on multi-level modeling techniques.

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Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach 15

Pre-simulation elaboration of heterogeneous systems: The Sys...

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15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： Aoun, Cédric Ben Andrade, Liliana Maehne, Torsten Pêcheux, François Louërat, Marie-Minerve Vachouxy, Alain Sorbonne Universités UPMC Univ Paris 06 CNRS UMR 7606 Paris France LSM Lausanne Switzerland

ISBN: (纸本)9781467373111

Designers of the upcoming digital-centric More-than-Moore systems are lacking a common design and simulation environment able to efficiently manage all the multi-disciplinary aspects of its components of various nature that closely interact with each other. A key to successful design and verification lies in a SystemC-based virtual prototyping environment that is able to simulate a complex heterogeneous system as a whole, for which each component is described and solved using the most appropriate Model of Computation (MoC). In this paper, we present a new generic MoC-independent elaboration scheme that aims at preparing a Virtual Prototype (VP) for simulation. It requires to check the correct composition of the system model through dimensional analysis, to explore the model structure to identify involved MoC and interfaces between MoCs, and to detect the underlying dependencies. Eventually, information extracted from the exploration allow the instantiation of MoC-specific solvers. To soundly handle the global model execution with a Discrete Event (DE) kernel as the main solver, synchronization mechanisms with master-slave semantics within the model structure are implicitly deduced. © 2015 IEEE.

关键词： Virtual prototyping

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VHDL implementation of self-timed 32-bit floating point multiplier with carry look ahead adder

VHDL implementation of self-timed 32-bit floating point mult...

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international conference on Advanced Communication, Control and Computing Technologies (ICACCCT)

作者： Salty Beohar Sandip Nemade Electronics and Communication Engineering Technocrats Institute of Technology (TIT) Bhopal India

ISBN: (纸本)9781467395465

A large number of computer applications(like computer Graphics, Control systems, modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating point designs. Considering that the synchronous architectures requires that that all clock events happen at the same time over the complete circuit which it not possible due to clock skew also the latency and throughput of the circuit are directly linked to the worst-case delay of the slowest element which increases the delay. Hence this paper presents self-timed carry look ahead adder based implementation of IEEE 754 32 bit floating point multiplier for FPGA devices. The simulation results shows that the proposed design has lower latency than synchronous design as well as lower power requirements.

关键词： Adders computers computer architecture Algorithm design and analysis Clocks simulation Latches

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Software Fault Tolerance for FPUs via Vectorization 15

Software Fault Tolerance for FPUs via Vectorization

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international conference on embedded computer systems architectures modeling and simulation

作者： Chen, Zhi Inagaki, Ryoichi Nicolau, Alexandru Veidenbaum, Alexander V. Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA

ISBN: (纸本)9781467373111

Future generation processors are expected to have high soft error rates and will require increased fault detection and fault tolerance. This work focuses on errors in execution units. Hardware or software duplication or triplication, parity, or residue codes could be used to detect errors in execution units. However, hardware duplication/triplication have significant area overhead and, in applications with high utilization of floating point units (FPU), very high energy cost. Software duplication/triplication of instructions also increases both execution time and energy consumption. This paper proposes to reduce the cost of redundant instruction execution in FPUs through vectorization. Duplicated or triplicated instructions and result comparisons can be packed by a compiler into vector instructions, such as SSE or AVX. Experimental results using hand vectorization on a variety of benchmarks show that, compared to error detection through scalar instruction duplication, vector mode redundant execution achieves 1.78x and 2.73x average speedup for SSE and AVX instructions, respectively. It also significantly reduces the energy consumption, by an average of 40% and 53%, respectively, for SSE and AVX. Thus the proposed technique enables error detection with no hardware cost and reduced time and energy overhead compared to brute-force scalar instruction duplication.

关键词： Streaming SIMD Extensions instruction Error detection energy consumption instruction execute software fault tolerance residue codes Replication Legal Executions compilers computer hardware Error analysis Fault tolerance execution time Defect detection

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Hardware-In-the-Loop simulation of UAV hexacopter for Chemical Hazard monitoring mission

Hardware-In-the-Loop Simulation of UAV hexacopter for Chemic...

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IEEE international conference on System Engineering and Technology

作者： Rendy Wandarosanza Bambang Riyanto Trilaksono Egi Hidayat Department of Electrical Engineering Institut Teknologi Bandung Bandung West Java Indonesia Institut Teknologi Bandung Bandung Jawa Barat ID

ISBN: (纸本)9781509050901

Field trial is a very critical stage and high risk in UAV development cycle. HILS is a computer-assisted simulation techniques used in the development and testing of complex embedded real-time systems. HILS has the ability to simulate UAV flight characteristics, sensor modeling, and modeling of actuators while communicating in real time with flight control hardware. HILS aims to test the reliability of UAV flight control hardware, integration test of Chemical monitoring systems, and tuning the control parameters. Advantages of using HILS are lower the development costs, improve safety, and streamline the development process. HILS provides development process without using actual UAV platform, but by using a mathematical equation to represent the UAV platform that will be used. HILS implement control system on Pixhawk then the output actuators used as model input. Hexacopter model will produce the attitude and position of hexacopter modeled as sensors model. The output of sensors model will be the input for computing the next control command of Pixhawk. HILS can be used to test the integration of UAV platform with Chemical sensor module to ensure Chemical monitoring missions can run well on the real situation.

关键词： Rotors Unmanned aerial vehicles Mathematical model Computational modeling Atmospheric modeling Earth Torque

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Rapid Prototyping and Design Space Exploration Methodologies for Many-Accelerator systems 25

Rapid Prototyping and Design Space Exploration Methodologies...

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25th international conference on Field Programmable Logic and Applications

作者： Sotiriou-Xanthopoulos, Efstathios Xydis, Sotirios Siozios, Kostas Economakos, George Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece

ISBN: (纸本)9781467381239

The ever-growing design complexity of modern embedded systems and the need for lower energy consumption have lead to design techniques which target to bridge the gap between the designer's productivity and the design complexity. In particular, Virtual Prototyping enables the system modeling and simulation in multiple abstraction levels, while the automated Design Space Exploration (DSE) targets to find optimized design solutions in a reasonable time. However, there is the need for more efficient techniques for prototyping and co-simulation, as the rapid simulation has become a stringent requirement. In addition, as emerging heterogeneous architectures expose even higher design complexity, typical DSE techniques may not achieve high-quality design solutions. Towards this direction, the proposed design flow introduces (a) a set of prototyping techniques which target to faster but accurate simulation, also supporting the system co-simulation with other environments, and (b) a number of DSE methodologies for high-complexity computation and communication architectures.

关键词： rapid prototyping Space Exploration DSE gene systems modelling embedded systems PROTOTYPE Design flow Optimal design simulating

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