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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Stavros Tripakis Aalto University University of California Berkeley

FMI (Functional Mockup Interface) is a standard for exchanging and co-simulating model components (called FMUs) coming from potentially different modeling formalisms, languages, and tools. Previous work has proposed a formal model for the co-simulation part of the FMI standard, and also presented two co-simulation algorithms which can be proven to have desirable properties, such as determinacy, provided the FMUs satisfy a formal contract. In this paper we discuss the principles for encoding different modeling formalisms, including state machines (both untimed and timed), discrete-event systems, and synchronous dataflow, as FMUs. The challenge is to bridge the various semantic gaps (untimed vs. timed, signals vs. events, etc.) that arise because of the heterogeneity between these modeling formalisms and the FMI API.

关键词： Semantics Computational modeling Yttrium Input variables Encoding Bridges Integrated circuit modeling

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Using VLIW softcore processors for image processing applications

Using VLIW softcore processors for image processing applicat...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Joost Hoozemans Stephan Wong Zaid Al-Ars Delft University of Technology Delft The Netherlands

The ever-increasing complexity of advanced high-resolution image processing applications requires innovative solutions to ensure addressing this issue efficiently and cost effectively. This paper discusses the utilization of reconfigurable general-purpose softcore processors in image processing applications such that hardware resources are efficiently utilized and at the same time ensure high image processing performance for the targeted application. Results show that the rVEX softcore processor can achieve remarkably better performance compared to the industry-standard Xilinx MicroBlaze (up to a factor of 3.2 times faster) on image processing applications.

关键词： Program processors VLIW Image processing Field programmable gate arrays computer architecture Convolution Computational modeling

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An interval algebra for multiprocessor resource allocation

An interval algebra for multiprocessor resource allocation

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Leandro Soares Indrusiak Piotr Dziurzanski Department of Computer Science University of York York UK

This paper presents an interval algebra created specifically to evaluate timing properties of multiprocessor systems. It models the application load as intervals, and considers allocation and scheduling as algebraic operations over those intervals, aiming to analyse the impact of resource allocation decisions on application response times or schedulability. The theoretical background is introduced informally, followed by the description of a reference implementation of the interval algebra in C++, aiming to appeal to the design practitioner rather than the formalist. Examples of the usage of the proposed algebra are also provided, showing its applicability to the performance evaluation of industrial systems implemented over bus-based and Network-on-Chip multiprocessor platforms. A particular design flow is highlighted, where the interval algebra is used as a fitness function in a genetic algorithm tailored to optimise resource allocation in hard real-time multiprocessors.

关键词： Resource management Algebra Real-time systems Computational modeling Calculus Load modeling Program processors

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FNOCEE: A framework for NoC evaluation by FPGA-based emulation

FNOCEE: A framework for NoC evaluation by FPGA-based emulati...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Daniel Pfefferkorn Achim Schmider Guillermo Payá-Vayá Martin Neuenhahn Holger Blume Institute of Microelectronic Systems Leibniz Universität Hannover Hannover Germany

This paper introduces FNOCEE, a framework for the evaluation of NoC-based many-cores systems by FPGA-based emulation. It uses a task graph-oriented approach to model applications, while a hardware-accelerated genetic algorithm is employed to find close-to-optimal solutions to the task mapping problem. The proposed genetic algorithm is analyzed in detail, e.g., in terms of mutation rate and number of elite individuals. In order to illustrate the framework's capabilities, several case studies have been performed, wherein scalability of relevant parallel applications is investigated with regard to the number and type of available processing cores and the generated traffic load as a result of inter-task communication.

关键词： computer architecture Genomics Bioinformatics Genetic algorithms Computational modeling Emulation Topology

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Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end

Multi-Domain SystemC model of 128-channel time-multiplexed n...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Kiki Wirianto Amir Zjajo Carlo Galuzzi Rene van Leuken Circuits and Systems Group Delft University of Technology Delft The Netherlands BMI Research Group Maastricht University Maastricht The Netherlands

A SystemC Multi-Domain Virtual Prototype (MDVP) framework provides multi-domain system integration of multi-electrode neural interface and a fast validation time, offering more efficient design process. In this paper, we propose efficient neuron cell, neuron tissue, and multi-channel neural interface front-end models implemented in a SystemC MDVP framework, which supports chemical, biological, and electrical domain modeling and simulation. The proposed model offers advantages for designers not only in reducing the design time, but also regarding the system integration. We make use of 8×16-channel front-end recording circuits to implement a 128-channel time-multiplexed neural interface front-end model. These models are verified with realistic simulation settings and appropriate input signals.

关键词： Neurons Integrated circuit modeling Electrodes Biological system modeling computer architecture Computational modeling Mathematical model

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HEVC in-loop filters GPU parallelization in embedded systems

HEVC in-loop filters GPU parallelization in embedded systems

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Diego F. de Souza Aleksandar Ilic Nuno Roma Leonel Sousa INESC-ID Universidade de Lisboa Lisbon Portugal

The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied devices. To circumvent this limitation, this paper proposes the exploitation of embedded GPU devices already equipping many state of the art SoCs to accelerate the HEVC in-loop filters (i.e. deblocking filter and sample adaptive offset). The presented approaches comprehensively exploit both fine and coarse-grained parallelization opportunities of these filters in an NVIDIA Tegra *** to the conducted experimental evaluation, the proposed approach showed to be a remarkable strategy to satisfy the real-time requirements of the HEVC decoder, being able to filter each Ultra HD 4K intra frame in less than 20 ms (about 50 fps).

关键词： Decoding Graphics processing units Standards Encoding Computational modeling Filtering computer architecture

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MCMG simulator: A unified simulation framework for CPU and graphic GPU

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JOURNAL OF computer AND SYSTEM SCIENCES 2015年第1期81卷 57-71页

作者： Ma, Jianliang Yu, Licheng Ye, John M. Chen, Tianzhou Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310003 Zhejiang Peoples R China

Accurate simulation is vital for the proper design and evaluation of any computing architecture. Researchers seek unified simulation frameworks that can model heterogeneous architectures like CPU and GPU devices and their interactions as computing patterns move toward heterogeneous era. In this paper, we introduce MCMG (Multi-CPU Multi-CPU) simulator, a cycle accurate, modular and open-source toolset that enables simulating x86 CPUs and Nvidia G80 like CPUs simultaneously. Targeting heterogeneous architectural exploration, MCMG supports fully configuration of multiple CPUs, CPUs and their memory sub-system. Not only CPUs, relative running frequency of each CPU can be also defined conveniently. simulation validation is demonstrated with a preliminary architectural exploration study. Then we present shared LLC access results of heterogeneous cores and show reasonable explanation. Finally, we conclude the job. (C) 2014 Elsevier Inc. All rights reserved.

关键词： MCMG (Multi-CPU Multi-CPU) simulator Heterogeneous multi-core architecture System validation

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A lightweight infrastructure for the dynamic creation and configuration of virtual platforms

A lightweight infrastructure for the dynamic creation and co...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Christian Sauer Hans-Peter Loeb Cadence Design Systems Munich Germany

Virtual prototypes leverage SystemC/TLM for simulating programmable platforms comprising 100s of modules. Their efficient creation and configuration is vital for acceptable turnaround times, e.g., during performance exploration or software development. Therefore, our lightweight infrastructure provides a factory creating designs from abstract descriptions of module instances, properties, and connections. Modules mark properties as creation or runtime parameters. The resulting generic design descriptions are usable by non-experts and enable front-ends. The infrastructure is a small C++ library that can be combined with existing SystemC/TLM models and simulation kernels. An industrial case study of a complex multiprocessor SoC shows a distinct productivity gain.

关键词： Production facilities Unified modeling language Prototypes Libraries Containers Runtime Green products

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Chip-independent Error Correction in main memories

Chip-independent Error Correction in main memories

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Mehrtash Manoochehri Michel Dubois Department of Electrical Engineering University of Southern California Los Angeles USA

Main memory reliability is an important concern in today's computer systems. Error Correction Codes (ECCs) improve memory reliability but have high area and energy overheads. Furthermore, ECCs cannot be easily applied to memories with wide chips such as stacked memories. In this paper, we introduce a new low-overhead error correction scheme, which can easily be applied to DRAM memories with wide devices. The scheme is called Chip-Independent Error Correction (CIEC) because it is independent of the memory chip width. Our simulation results in the context of transient faults show that CIEC has only 4.5% energy overhead, 0.5% performance overhead, and 0.7% area overhead on the processor chip as compared to a non-ECC DIMM while its reliability is much higher than the reliability of non-ECC DIMMs.

关键词： Reliability Error correction codes Memory management Registers Error correction Computational modeling computers

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Modana: An Integrated Framework for modeling and Analysis of Energy-Aware CPSs 39

Modana: An Integrated Framework for Modeling and Analysis of...

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39th IEEE Annual international computer Software and Applications conference Workshops (COMPSAC)

作者： Cheng, Bei Wang, Xiao Liu, Jufu Du, Dehui East China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai 200062 Peoples R China

ISBN: (纸本)9781467365635

Cyber-Physical systems (CPSs) as advanced embedded systems integrating computation with physical process are increasingly penetrating into our life. modeling and analysis for such systems closely involved with us are actively researched. A current challenging problem is how to take advantages of existing technologies like SysML/MARTE, Modelica and Statistical Model Checking (SMC) through effective integration. Moreover, the lack of efficient methodologies or tools for modeling and analysis of CPSs makes the gap between design and analysis models hard to bridge. To solve these problems, we present a framework named Modana to achieve an integrated process from modeling with SysML/MARTE to analysis with SMC for CPSs in terms of Non-Functional Properties (NFP) such as time, energy, etc. Functional Mock-up Interface (FMI), as a connecting link between modeling and analysis, plays a major role in coordinating various tools for co-simulation to generate traces as the input of statistical model checker. To demonstrate the capability of Modana framework, we model energy-aware buildings as a case study, and discuss the analysis on energy consumption in different scenarios.

关键词： cyber-physical systems SysML/MARTE functional mock-up interface statistical model checking energy-aware buildings

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