Main memory reliability is an important concern in today's computersystems. Error Correction Codes (ECCs) improve memory reliability but have high area and energy overheads. Furthermore, ECCs cannot be easily app...
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Main memory reliability is an important concern in today's computersystems. Error Correction Codes (ECCs) improve memory reliability but have high area and energy overheads. Furthermore, ECCs cannot be easily applied to memories with wide chips such as stacked memories. In this paper, we introduce a new low-overhead error correction scheme, which can easily be applied to DRAM memories with wide devices. The scheme is called Chip-Independent Error Correction (CIEC) because it is independent of the memory chip width. Our simulation results in the context of transient faults show that CIEC has only 4.5% energy overhead, 0.5% performance overhead, and 0.7% area overhead on the processor chip as compared to a non-ECC DIMM while its reliability is much higher than the reliability of non-ECC DIMMs.
Cyber-Physical systems (CPSs) as advanced embeddedsystems integrating computation with physical process are increasingly penetrating into our life. modeling and analysis for such systems closely involved with us are ...
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ISBN:
(纸本)9781467365635
Cyber-Physical systems (CPSs) as advanced embeddedsystems integrating computation with physical process are increasingly penetrating into our life. modeling and analysis for such systems closely involved with us are actively researched. A current challenging problem is how to take advantages of existing technologies like SysML/MARTE, Modelica and Statistical Model Checking (SMC) through effective integration. Moreover, the lack of efficient methodologies or tools for modeling and analysis of CPSs makes the gap between design and analysis models hard to bridge. To solve these problems, we present a framework named Modana to achieve an integrated process from modeling with SysML/MARTE to analysis with SMC for CPSs in terms of Non-Functional Properties (NFP) such as time, energy, etc. Functional Mock-up Interface (FMI), as a connecting link between modeling and analysis, plays a major role in coordinating various tools for co-simulation to generate traces as the input of statistical model checker. To demonstrate the capability of Modana framework, we model energy-aware buildings as a case study, and discuss the analysis on energy consumption in different scenarios.
The development of non-blocking code is difficult; developers must ensure the progress of an operation on shared memory despite conflicting operations. Managing this shared memory in a non-blocking fashion is even mor...
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The development of non-blocking code is difficult; developers must ensure the progress of an operation on shared memory despite conflicting operations. Managing this shared memory in a non-blocking fashion is even more problematic. The non-blocking property guarantees that progress is made toward the desired operation in a finite amount of time. We present a framework that implements memory reclamation and progress assurance for code that follows the semantics of our framework. This reduces the effort required to implement non-blocking, and more specifically wait-free, algorithms. We also present a library that demonstrates the ease with which wait-free algorithms can be implemented using our framework.
Noise reduction is one of the most fundamental digital image processing challenges. On mobile devices, proper solutions for this task can significantly increase the output image quality making the use of a camera even...
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Noise reduction is one of the most fundamental digital image processing challenges. On mobile devices, proper solutions for this task can significantly increase the output image quality making the use of a camera even more attractive for customers. The main challenge is that the processing time and energy efficiency must be optimized, since the response time and the battery life are critical factors for all mobile applications. To identify the solutions that maximizes the real-time performance, we compare several different implementations in terms of computational performance and energy efficiency. Specifically, we compare the OpenCL based design with multithreaded and NEON accelerated implementations and analyze them on the mobile platform. Based on the results of this study, the OpenCL framework provides a viable energy efficient alternative for implementing computer vision algorithms.
The AXIOM project (Agile, eXtensible, fast I/O Module) aims at researching new software/hardware architectures for the future Cyber-Physical systems (CPSs). These systems are expected to react in real-time, provide en...
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The AXIOM project (Agile, eXtensible, fast I/O Module) aims at researching new software/hardware architectures for the future Cyber-Physical systems (CPSs). These systems are expected to react in real-time, provide enough computational power for the assigned tasks, consume the least possible energy for such task (energy efficiency), scale up through modularity, allow for an easy programmability across performance scaling, and exploit at best existing standards at minimal costs.
This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained s...
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This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained streaming applications and multiple latency-constrained feedback control applications onto a multi-processor platform running under a Time-Division Multiple-Access (TDMA) policy. The main objective of the proposed method is to reduce resource usage while meeting constraints from both these two domains (i.e., throughput and latency constraints). We show by experiments that the overall resource usage for this mapping problem can be reduced by distributing the allocated resource (i.e., TDMA slots) to the control applications over the TDMA wheel instead of allocating consecutive slots.
We present a novel data-driven agent-based modeling framework to study innovation diffusion. Our first step is to learn a model of individual agent behavior from individual adoption characteristics. We then construct ...
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Task migration has been applied as an efficient mechanism to handle faulty processing elements (PEs) in Multi-processor systems-on-Chip (MPSoCs). However, current task migration solutions are either implemented or emu...
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Task migration has been applied as an efficient mechanism to handle faulty processing elements (PEs) in Multi-processor systems-on-Chip (MPSoCs). However, current task migration solutions are either implemented or emulated in software, compromising intrinsically the predictability and degrading the system robustness. Moreover, the initial placement and mapping of the tasks in the MPSoC plays an important role in minimising the task migration overhead and overall system energy. This paper proposes a hardware-based task migration scheme for MPSoC systems, offering better predictability as well as an improved method of fault tolerance. The proposed scheme intelligently generates an initial placement for the tasks with improved fault tolerance and stores these mappings on a hash map, which is looked up at run-time as and when faults occur. Compared with the state-of-the-art, our scheme performs up to 1500× faster task migration without any significant overheads.
Modern embeddedsystems are now capable of executing complex and demanding applications that are often based on large data structures. The design of the critical data structures of the application affects the performa...
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Modern embeddedsystems are now capable of executing complex and demanding applications that are often based on large data structures. The design of the critical data structures of the application affects the performance and the memory requirements of the whole system. Dynamic Data Structure Refinement methodology provides optimizations, mainly in list and array data structures, which are based on the application's features and access patterns. In this work, we extend various aspects of the methodology: First, we integrate radix tree optimizations. Then, we provide a set of platform-aware data structure implementations, for performing optimizations based on the hardware features. The extended methodology is evaluated using a wide set of synthetic and real-world benchmarks, in which we achieved performance and memory trade-offs up to 29.6%. Additionally, Pareto optimal data structure implementations that were not available by the previous methodology, are identified with the extended one.
Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This pre...
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Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The evaluation for the ARM Cortex-A9 processor shows that the proposed approach is able to achieve a high accuracy. In comparison to hardware power measurements obtained from the OMAP4460 chip on the PandaBoard, the ESL estimation error is below 5%.
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