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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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5th international Workshop on Performance modeling, Benchmarking and simulation, PMBS 2014

5th International Workshop on Performance Modeling, Benchmar...

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5th international Workshop on Performance modeling, Benchmarking, and simulation of High Performance Computing systems, PMBS 2014

ISBN: (纸本)9783319172477

The proceedings contain 14 papers. The special focus in this conference is on High Performance Computing systems. The topics include: Algebraic multigrid on a dragonfly network;performance evaluation of scientific applications on POWER8;a standard application suite for measuring hardware accelerator performance;a CUDA implementation of the high performance conjugate gradient benchmark;performance analysis of a high-level abstractions-based hydrocode on future computing systems;insight into application performance using application-dependent characteristics;a practical tool for architectural and program analysis;modeling stencil computations on modern HPC architectures;performance modeling of the HPCG benchmark;on the performance prediction of BLAS-based tensor contractions;assessing general-purpose algorithms to cope with fail-stop and silent errors;a case for epidemic fault detection and group membership in HPC storage systems;analysis of the tradeoffs between energy and run time for multilevel checkpointing and on the energy proportionality of distributed NoSQL data stores.

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Physical design aware system level synthesis of hardware

Physical design aware system level synthesis of hardware

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Nasim Farahini Ahmed Hemani Hassan Sohofi Shuo Li KTH Royal Institute of Technology Sweden

In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.

关键词： Measurement Standards Physical design Hardware Fabrics Space exploration Computational modeling

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Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach

Pre-simulation elaboration of heterogeneous systems: The Sys...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Cédric Ben Aoun Liliana Andrade Torsten Maehne François Pêcheux Marie-Minerve Louërat Alain Vachouxy CNRS UPMC Univ Paris 06 Paris France Ecole Polytechnique Federale de Lausanne Lausanne VD CH

Designers of the upcoming digital-centric More-than-Moore systems are lacking a common design and simulation environment able to efficiently manage all the multi-disciplinary aspects of its components of various nature that closely interact with each other. A key to successful design and verification lies in a SystemC-based virtual prototyping environment that is able to simulate a complex heterogeneous system as a whole, for which each component is described and solved using the most appropriate Model of Computation (MoC). In this paper, we present a new generic MoC-independent elaboration scheme that aims at preparing a Virtual Prototype (VP) for simulation. It requires to check the correct composition of the system model through dimensional analysis, to explore the model structure to identify involved MoC and interfaces between MoCs, and to detect the underlying dependencies. Eventually, information extracted from the exploration allow the instantiation of MoC-specific solvers. To soundly handle the global model execution with a Discrete Event (DE) kernel as the main solver, synchronization mechanisms with master-slave semantics within the model structure are implicitly deduced.

关键词： Computational modeling Mathematical model Synchronization Semantics Kernel Ports (computers) Optical sensors

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GPU implementation of an anisotropic Huber-L1 dense optical flow algorithm using OpenCL

GPU implementation of an anisotropic Huber-L1 dense optical ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Duygu Büyükaydin Toygar Akgün ASELSAN Transportation Security Energy and Automation Systems (UGES) Business Sector Ankara Turkey

Optical flow estimation aims at inferring a dense pixel-wise correspondence field between two images or video frames. It is commonly used in video processing and computer vision applications, including motion-compensated frame processing, extracting temporal features, computing stereo disparity, understanding scene context/dynamics and understanding behavior. Dense optical flow estimation is a computationally complex problem. Fortunately, a wide range of optical flow estimation algorithms are embarrassingly parallel and can efficiently be accelerated on GPUs. In this work we discuss a massively multi-threaded GPU implementation of the anisotropic Huber-L1 optical flow estimation algorithm using OpenCL framework, which achieves per frame execution time speed-up factors up to almost 300×. Overall algorithm flow, GPU specific implementation details and performance results are presented.

关键词： Optical imaging Kernel Graphics processing units Biomedical optical imaging Estimation Computational modeling Geometrical optics

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Uniting Academic Achievements on Performance Analysis with Industrial Needs 12th

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12th international conference on Quantitative Evaluation of systems (QEST)

作者： Theelen, Bart Hooman, Jozef Embedded Syst Innovat TNO Eindhoven Netherlands Radboud Univ Nijmegen NL-6525 ED Nijmegen Netherlands

ISBN: (纸本)9783319222646;9783319222639

In our mission to advance innovation by industrial adoption of academic results, we perform many projects with high-tech industries. Favoring formal methods, we observe a gap between industrial needs in performance modeling and the analysis capabilities of formal methods for this goal. After clarifying this gap, we highlight some relevant deficiencies for state-of-the-art quantitative analysis techniques (focusing on model checking and simulation). As an ingredient to bridging the gap, we propose to unite domain-specific industrial contexts with academic performance approaches through Domain Specific Languages (DSLs). We illustrate our vision with examples from different high-tech industries and discuss lessons learned from the migration process of adopting it.

关键词： Domain specific languages Model checking Performance analysis Performance modelling Quantitative analysis simulation

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A high-level DRAM timing, power and area exploration tool

A high-level DRAM timing, power and area exploration tool

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Omar Naji Christian Weis Matthias Jung Norbert Wehn Andreas Hansson Microelectronic Systems Design Research Group University of Kaiserslautern Kaiserslautern Germany ARM Ltd. Cambridge United Kingdom

In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Evaluating the impact of DRAM design decisions therefore requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload which requires a full system simulator, running a complete software stack. In this paper, we introduce DRAMSpec, an open source high-level DRAM bank modeling tool. As major contribution, we move the DRAM modeling abstraction level from detailed circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications and use cases. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row buffer size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16% DRAM performance improvement and 13% DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures for which no datasheets are available.

关键词： Random access memory Integrated circuit modeling computer architecture Performance evaluation Computational modeling Delays

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HARPA: Solutions for dependable performance under physically induced performance variability

HARPA: Solutions for dependable performance under physically...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dimitrios Rodopoulos Simone Corbetta Giuseppe Massari Simone Libutti Francky Catthoor Yiannakis Sazeides Chrysostomos Nicopoulos Antoni Portero Etienne Cappe Radim Vavrík Vít Vondrák Dimitrios Soudris Federico Sassi Agnes Fritsch William Fornaciari ICCS MicroLab Greece SSET - imec KU Leuven Belgium DEIB POLIMI Italy Ξ / multiCAL UCY Cyprus VSB-TUO IT4Innovations Czech Republic Thales Group France Henesis s.r.l. Italy

Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need to be carefully considered so that the dependability of digital systems can be guaranteed. Already, architectures contain many mechanisms that detect and correct physically induced reliability violations. In many cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper discusses the FP7-612069-HARPA project of the European Commission and its approach towards dependable performance. This project provides solutions for performance variability mitigation, under the run time presence of fabric variability/aging and built-in reliability, availability and serviceability (RAS) techniques. In this paper, we briefly present and discuss modeling and mitigation techniques developed within HARPA, covering many abstractions of digital system design: from the transistor to the application layer.

关键词： Computational modeling Reliability computers Fabrics computer architecture Europe Market research

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Dynamic re-vectorization of binary code

Dynamic re-vectorization of binary code

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Nabil Hallou Erven Rohou Philippe Clauss Alain Ketterlin Team ALF INRIA Rennes France Team CAMUS University of Strasbourg France

In many cases, applications are not optimized for the hardware on which they run. Several reasons contribute to this unsatisfying situation, including legacy code, commercial code distributed in binary form, or deployment on compute farms. In fact, backward compatibility of ISA guarantees only the functionality, not the best exploitation of the hardware. In this work, we focus on maximizing the CPU efficiency for the SIMD extensions and propose to convert automatically, and at runtime, loops vectorized for an older version of the SIMD extension to a newer one. We propose a lightweight mechanism, that does not include a vectorizer, but instead leverages what a static vectorizer previously did. We show that many loops compiled for x86 SSE can be dynamically converted to the more recent and more powerful AVX; as well as, how correctness is maintained with regards to challenges such as data dependences and reductions. We obtain speedups in line with those of a native compiler targeting AVX. The re-vectorizer is implemented inside a dynamic optimization platform; it is completely transparent to the user, does not require rewriting binaries, and operates during program execution.

关键词： Optimization Hardware Computational modeling Registers computer architecture Binary codes Heuristic algorithms

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Parallel program = operator + schedule + parallel data structure

Parallel program = operator + schedule + parallel data struc...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Keshav Pingali University of Texas at Austin Austin TX US

Summary form only given. Multicore and manycore processors are now ubiquitous, but parallel programming remains as difficult as it was 30-40 years ago. In this talk, I will argue that these problems arise largely from the computation-centric abstractions that we currently use to think about parallelism. In their place, I will propose a novel data-centric foundation for parallel programming called the operator formulation in which algorithms are described in terms of unitary actions on data structures. This data-centric view of parallel algorithms shows that a generalized form of data-parallelism called amorphous data-parallelism is ubiquitous even in complex, irregular graph applications such as mesh generation and partitioning algorithms, graph analytics, and machine learning applications. Binding time considerations provide a unification of parallelization techniques ranging from static parallelization to speculative parallelization. We have built a system called Galois, based on these ideas, for exploiting amorphous data-parallelism on multicores and GPUs. I will present experimental results from our group as well as from other groups that are using the Galois system.

关键词： Multicore processing Program processors Parallel programming computer languages Computational modeling Data models

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Framework for parameter analysis of FPGA-based image processing architectures

Framework for parameter analysis of FPGA-based image process...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Marc Reichenbach Benjamin Pfundt Dietmar Fey Friedrich-Alexander-University Erlangen-Nürnberg (FAU) Computer Architecture Erlangen Germany

Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the description of stencil codes. A promising approach in embedded systems is to use the massively parallel computation power of an FPGA for this kind of algorithms. This not only speeds up processing time, if the FPGA is directly placed inside the image acquisition unit forming a smart camera, but also reduces or even eliminates the PC based hardware which saves space and power. However, most designers begin from scratch when they have to implement stencil computations into smart cameras. This leads to a not fully utilized FPGA because the most efficient usage of the given resources is only secondary alongside functional correctness. Therefore, we are presenting in this paper a framework for stencil code applications which immediately delivers the best architecture regarding prominent resource criteria. An analytical model is used to find an optimized parameter set (degree of parallelism, usage of buffers, etc.) for a highly flexible FPGA implementation. A graphical tool allows to further evaluate the effects of certain parameters. Our results show, that we are able to create an optimized hardware architecture for this application domain.

关键词： computer architecture Field programmable gate arrays Parallel processing Hardware Analytical models Bandwidth Throughput

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