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A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models

A power estimation technique for cycle-accurate higher-abstr...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Efstathios Sotiriou-Xanthopoulos G. Shalina Percy Delicia Peter Figuli Kostas Siozios George Economakos Jürgen Becker School of Electrical and Computer Engineering National Technical University of Athens Athens Greece Institute for Information Processing Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE Institute for Information Processing Karlsruhe Institute of Technology Karlsruhe Germany

Due to the ever-increasing complexity of embedded system design and the need for rapid system evaluations in early design stages, the use of simulation models known as Virtual Platforms (VPs) has been of utmost importance as they enable system modeling at higher abstraction levels. Since a typical VP features multiple interdependent components, VP libraries have been utilized in order to provide off-the-shelf models of commonly-used hardware components, such as CPUs. However, CPU power estimation is not adequately supported by existing VP libraries. In addition, existing power characterization techniques require architectural details which are not always available in early design stages. To address this issue, this paper proposes a technique for power annotation of CPU models targeting SystemC/TLM libraries in order to enable the accurate power estimation at higher abstraction levels. By using a set of benchmarks on a power-annotated SystemC/TLM model of Xilinx Microblaze soft-processor, it is shown that the proposed approach can achieve accurate power estimation in comparison to the real-system power measurements as the estimation error ranges from 0.47% up to 6.11% with an average of 2%.

关键词： Estimation Computational modeling Power measurement Libraries Power demand Predictive models Software

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Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator

Efficient dual-ISA support in a retargetable, asynchronous D...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Tom Spink Harry Wagstaff Björn Franke Nigel Topham The University of Edinburgh Edinburgh Edinburgh GB

Dynamic Binary Translation (DBT) allows software compiled for one Instruction Set Architecture (ISA) to be executed on a processor supporting a different ISA. Some modern DBT systems decouple their main execution loop from the built-in Just-In-Time (JIT) compiler, i.e. the JIT compiler can operate asynchronously in a different thread without blocking program execution. However, this creates a problem for target architectures with dual-ISA support such as ARM/THUMB, where the ISA of the currently executed instruction stream may be different to the one processed by the JIT compiler due to their decoupled operation and dynamic mode changes. In this paper we present a new approach for dual-ISA support in such an asynchronous DBT system, which integrates ISA mode tracking and hot-swapping of software instruction decoders. We demonstrate how this can be achieved in a retargetable DBT system, where the target ISA is not hard-coded, but a processor-specific module is generated from a high-level architecture description. We have implemented ARM V5T support in our DBT and demonstrate execution rates of up to 1148 MIPS for the SPEC CPU 2006 benchmarks compiled for ARM/THUMB, achieving on average 192%, and up to 323%, of the speed of QEMU, which has been subject to intensive manual performance tuning and requires significant low-level effort for retargeting.

关键词： Thumb Decoding computer architecture Computational modeling Target tracking Instruction sets Registers

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DyMeP: An infrastructure to support Dynamic Memory binding for runtime mapping in CGRAs 28

DyMeP: An infrastructure to support Dynamic Memory binding f...

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28th international conference on VLSI Design (VLSID) / 14th international conference on embedded systems

作者： Tajammul, Muhammad Adeel Jafri, S. M. A. Ellerve, Peeter Hemani, Ahmed Tenhunen, Hannu Plosila, Juha Royal Inst Technol Sch ICT Stockholm Sweden Tallinn Univ Technol Dept Comp Engn Tallinn Estonia Univ Turku ECEC lab SF-20500 Turku Finland

ISBN: (纸本)9781479966585

Coarse Grained Reconfigurable architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications. Commonly, CGRAs are composed of a computation layer (that performs computations) and a memory layer (that provides data and configware to the computation layer). Tempted by higher platform utilization and reliability, recently proposed CGRAs offer dynamic application remapping (for the computation layer). Distributed scratch pad (compiler programmed) memories offer high data rates, predictability and low the power consumption (compared to caches). Therefore, the distributed scratchpad memories are emerging as preferred implementation alternative for the memory layer in recent CGRAs. However, the scratchpad memories are programmed at compile time, and do not support dynamic application remapping. The existing solutions that allow dynamic application remapping either rely on fat binaries (that significantly enhance configuration memory requirements) or consider a centralized memory. To extract the benefits of both runtime remapping and distributed scratchpad memories, we present a design framework called DyMeP. DyMeP relies on late binding and provides the architectural support to dynamically remap data in CGRAs. Compared to the state of the art, the proposed technique reduces the configuration memory requirements (needed by fat binary solutions) and supports distributed shared scratchpad memory. Synthesis/simulation results reveal that DyMeP promises a significant (up to 60%) reduction in configware size at the cost of negligible additional overheads (less then 1%).

关键词： distributed shared memory systems reconfigurable architectures storage management CGRAs DyMeP coarse grained reconfigurable architectures compiler programmed memories computation layer distributed shared scratchpad memories dynamic application remapping dynamic memory binding fat binaries memory layer runtime mapping Delays Dynamic scheduling Hardware Memory management Routing Runtime Synchronization CGRA Coarse Grained Reconfigurable Architecture Dynamic Memory Binding NOC Network on Chip circuit switched network on chip late binding relative addressing Coarse-grained Reconfigurable Architecture Store management Late binding distributed shared memory systems Runtime scratchpad Reconfigurable architectures network-on-chip dynamic scheduling Memory computer hardware Network routing

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Examining recent many-core architectures and programming models using SHOC 6

Examining recent many-core architectures and programming mod...

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6th international Workshop in Performance modeling, Benchmarking and simulation of High Performance computer systems, PMBS 2015 - Held as part of the 27th ACM/IEEE international conference for High Performance Computing, Networking, Storage and Analysis, SC 2015

作者： Lopez, M. Graham Young, Jeffrey Meredith, Jeremy S. Roth, Philip C. Horton, Mitchel Vetter, Jeffrey S. Oak Ridge National Laboratory Computer Science and Mathematics Division Oak RidgeTN37831 United States Georgia Institute of Technology School of Computer Science AtlantaGA30332 United States National Institute for Computational Sciences University of Tennessee-Knoxville KnoxvilleTN237996 United States

ISBN: (纸本)9781450340090

The Scalable HeterOgeneous Computing (SHOC) benchmark suite was released in 2010 as a tool to evaluate the sta- bility and performance of emerging heterogeneous architec- Tures and to compare different programming models for com- pute devices used in those architectures. Since then, high- performance computing (HPC) system architectures have increasingly incorporated both discrete and fused multi-core and many-core processors. The TOP500 list illustrates this trend: heterogeneous systems grew from a 3.4% to 18.0% share of the list between June 2010 and June 2015. Not only are there more heterogeneous systems on the TOP500 list today, those machines are responsible for a dispropor- Tionately large percentage of list's aggregate performance: As of June 2015, the performance share for heterogeneous systems has grown to 33.7%. Part of this shift toward heterogeneous architectures has stemmed from new products in the hardware accelerator market, such as Intel's Xeon Phi coprocessor, and improve- ments in the approaches for programming such accelerators. Existing approaches such as CUDA and OpenCL have be- come more powerful and easy to use, and directive-based programming models such as OpenACC, OpenMP 4.0, and Intel's Language Extensions for Offload (LEO) are rapidly gaining user acceptance. The benefits of these hardware and software advances are not limited to HPC;other problem domains such as \big data" are reaping the rewards also. The original SHOC benchmarks had adequate support for Notice of Copyright CUDA and OpenCL for graphics processing units, but did not support more recent programming models and devices. We extended SHOC to support evaluation of recent het- erogeneous architectures and programming models such as OpenACC and LEO, and we added new benchmarks to in- crease SHOC's application domain coverage. In this pa- per, we describe our modifications to the stock SHOC dis- Tribution and present several examples of using our aug- mented version of SHOC for

关键词： Benchmarking

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Software fault tolerance for FPUs via vectorization

Software fault tolerance for FPUs via vectorization

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Zhi Chen Ryoichi Inagaki Alexandru Nicolau Alexander V. Veidenbaum Department of Computer Sciences University of California Irvine California

Future generation processors are expected to have high soft error rates and will require increased fault detection and fault tolerance. This work focuses on errors in execution units. Hardware or software duplication or triplication, parity, or residue codes could be used to detect errors in execution units. However, hardware duplication/triplication have significant area overhead and, in applications with high utilization of floating point units (FPU), very high energy cost. Software duplication/ triplication of instructions also increases both execution time and energy consumption. This paper proposes to reduce the cost of redundant instruction execution in FPUs through vectorization. Duplicated or triplicated instructions and result comparisons can be packed by a compiler into vector instructions, such as SSE or AVX. Experimental results using hand vectorization on a variety of benchmarks show that, compared to error detection through scalar instruction duplication, vector mode redundant execution achieves 1.78× and 2.73× average speedup for SSE and AVX instructions, respectively. It also significantly reduces the energy consumption, by an average of 40% and 53%, respectively, for SSE and AVX. Thus the proposed technique enables error detection with no hardware cost and reduced time and energy overhead compared to brute-force scalar instruction duplication.

关键词： Hardware Registers Computational modeling Program processors Energy consumption computers

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Power optimizations for transport triggered SIMD processors

Power optimizations for transport triggered SIMD processors

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Joonas Multanen Timo Viitanen Henry Linjamäki Heikki Kultala Pekka Jääskeläinen Jarmo Takala Lauri Koskinen Jesse Simonsson Heikki Berg Kalle Raiskila Tommi Zetterman Tampere University of Technology Finland University of Turku Finland Nokia Technologies LTD Finland

Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper's focus is on the RTL and microarchitecture level power optimizations applied to the design. Using semiautomated interconnection network and register file optimization algorithm, up to 27% of power savings were achieved. Using this as a baseline and applying register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to 26% of power and energy savings could be achieved with only a 3% area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve approximately 18% power improvement in comparison to a VLIW-like architecture by utilizing optimizations unique to transport triggered architectures.

关键词： Program processors computer architecture Optimization Radio frequency VLIW Registers Computational modeling

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3D-stacked many-core architecture for biological sequence analysis problems

3D-stacked many-core architecture for biological sequence an...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Pei Liu Ahmed Hemani Kolin Paul Dept. of Electronic Systems KTH Royal Institute of Technology Stockholm Sweden

Sequence analysis plays critical role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70% of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array (CGRA) we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of 68 mm2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than any existed hardware accelerators for at least 39 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.

关键词： Biology Sequences computer architecture Databases Bioinformatics Computational modeling Kernel

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MCMG simulator: A unified simulation framework for CPU and graphic GPU

MCMG simulator: A unified simulation framework for CPU and g...

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14th IEEE international conference on High Performance Computing and Communications (HPCC) / IEEE 9th international conference on embedded Software and systems (ICESS)

作者： Ma, Jianliang Yu, Licheng Ye, John M. Chen, Tianzhou Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310003 Zhejiang Peoples R China

Accurate simulation is vital for the proper design and evaluation of any computing architecture. Researchers seek unified simulation frameworks that can model heterogeneous architectures like CPU and GPU devices and their interactions as computing patterns move toward heterogeneous era. In this paper, we introduce MCMG (Multi-CPU Multi-CPU) simulator, a cycle accurate, modular and open-source toolset that enables simulating x86 CPUs and Nvidia G80 like CPUs simultaneously. Targeting heterogeneous architectural exploration, MCMG supports fully configuration of multiple CPUs, CPUs and their memory sub-system. Not only CPUs, relative running frequency of each CPU can be also defined conveniently. simulation validation is demonstrated with a preliminary architectural exploration study. Then we present shared LLC access results of heterogeneous cores and show reasonable explanation. Finally, we conclude the job. (C) 2014 Elsevier Inc. All rights reserved.

关键词： MCMG (Multi-CPU Multi-CPU) simulator Heterogeneous multi-core architecture System validation

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Generating ASIPs with reduced number of connections to the register-file

Generating ASIPs with reduced number of connections to the r...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Yosi Ben Asher Irina Lipov Vladislav Tartakovsky Dror Tiv CS. University of Haifa Israel

We propose automatic synthesis of application specific instruction set processors (ASIPs). We use pipeline execution of multi-op machine-instructions, e.g., *(reg1*reg2) = (*reg3)+ (*reg4) (C-syntax) an instruction with three memory pipeline stages and two arithmetic stages. The problem is, for a given set of loops, to find a pipeline configuration and a multi-op ISA that maximizes the IPC (instructions per cycle) while minimizing the resource usage and the cost of interconnections to the register-file of the resulting CPU. The algorithm is based on finding an efficient cover of a large graph by a small set of convex sub-graphs gis that are consistent with a given set of pipeline units. Unlike previous works, gis are not synthesized to circuits that are executed in a co-processor mode but rather both gis and the rest of the program are executed by the same set of multiop pipeline units. In this way we eliminate the overhead associated with the co-processor mode of regular ASIPs but maintain high values of IPC of these ASIPs. Once the pipeline configuration and the cover g 1 ∪ ... ∪ g n = G has been computed the Verilog RTL of the corresponding CPU (extended with branch instructions) is generated and synthesized to FPGA. The results show that, for a set of selected kernels, the resulting ASIP (called Ocpu) obtains higher IPC values compare to an equivalent compilation to an ARM cpu while obtaining similar clock frequencies.

关键词： Pipelines Computational modeling computer architecture Registers Central Processing Unit System-on-chip computers

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High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers

High-level synthesizable dataflow MapReduce accelerator for ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dionysios Diamantopoulos Christoforos Kachris School of Electrical and Computer Engineering National Technical University of Athens Greece Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece Athens Information Technology (AIT)

Manipulating big-data entries of emerging server workloads requires a design paradigm shift towards more aggressive system-level architecture solutions. From software perspective, the MapReduce framework is a prominent parallel data processing tool as the volume of data to analyze grows rapidly. FPGAs can be used to accelerate the processing of data and reduce significantly the power consumption. However, FPGAs have not been deployed in data centers due to the high programming complexity of hardware. In this paper we present HLSMapReduceFlow, i.e. a novel reconfigurable MapReduce accelerator that can be scaled-up to data centers and it can speedup the processing of Map computation kernels, while promising minimum energy footprint and high programming efficiency due to the use of HLS. We propose the complete decoupling of MapReduce's tasks data-paths to distinct buses, accessed from individual processing engines. Such a dataflow approach implies a holistic C/C++ to RTL domain-level MapReduce transition. In this work, we further extent HLS tools, with systematic source-to-source code annotation of HLS optimization directives, by adding as a state-of-art system-level implementation toolflow. The proposed architecture is implemented, mapped and evaluated to a Virtex-7 FPGA and shows that the proposed scheme can achieve up to 4.3× overall throughput improvement in MapReduce applications, while offering two orders of magnitude power/energy improvements compared to a high-end multi-core processor.

关键词： computer architecture Field programmable gate arrays Hardware Acceleration Computational modeling computers Servers

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