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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2832 条记录，以下是741-750 订阅

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Intelligent simulation Models based on Business Rules Approach in Banking Sector (WIP) 15

Intelligent Simulation Models based on Business Rules Approa...

引用

simulation Multiconference

作者： Roman R. Veynberg Aleksandra Varfolomeeva Kseniya Grigoryeva Plekhanov Russian University of Economics

ISBN: (纸本)9781510810594

In this paper, we discuss business rules management systems (BRMS) and their use in bank scoring models. Business rules are considered as an effective tool in determination of trustworthiness and solvency of borrowers, taking into account their socio-demographic and personal characteristics. This article will be informative for scientists in applied IT field, finance, banking, as well as for practicing risk managers and insurers.

关键词： BRMS Business rules Scoring Global rule flow embedded rule flow Credits Bank client Intelligent system Credits Intelligent systems Scoring Scoring Business Intelligent simulation banking Superelevation WIPF1 gene Insurance Carriers

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Vehicle-Hardware-In-The-Loop System for ADAS Prototyping and Validation 14

Vehicle-Hardware-In-The-Loop System for ADAS Prototyping and...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Galko, Clement Rossi, Romain Savatier, Xavier Inst Rech Syst Elect Embarques IRSEEM St Etienne France

ISBN: (纸本)9781479937707

This paper introduces an innovative system easing prototyping and validation of Advanced Driver Assistance systems (ADAS) for automotive applications. This system, based on a chassis-dynamometer and a multi-sensor simulation software, act as a virtual reality platform for intelligent vehicle. This system allows to test and validate complex ADAS systems under various simulated environmental conditions and scenario without the cost, complexity and hazard associated with test-drives. It can also be used early in the design process to test and validate the integration of multiple ADAS in a vehicle. This system is being used for the Virtual Testing applications in the DESERVE 1 project.

关键词： Advanced Driver Assistance System simulation Vehicle Hardware In The Loop DESERVE

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Combining Application Adaptivity and System-wide Resource Management on Multi-Core Platforms 14

Combining Application Adaptivity and System-wide Resource Ma...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Massari, Giuseppe Paone, Edoardo Bellasi, Patrick Palermo, Gianluca Zaccaria, Vittorio Fornaciari, William Silvano, Cristina Politecn Milan DEIB I-20133 Milan Italy

ISBN: (纸本)9781479937707

To better exploit the capabilities offered by multicore high-end embedded systems, new parallel programming paradigms, such as OpenCL, combined with effective resource management should be adopted. However, dealing with mixed workloads and time varying scenarios is still an open problem. This paper addresses such challenges by exploiting the synergy between Design Space Exploration and Run-Time Resource Management to achieve effective and flexible system-wide application adaptivity. The proposed approach and related toolset have been validated on a multi-core NUMA platform, showing significant improvements in terms of QoS and resource utilization compared to conventional application-level optimization strategies.

关键词： embedded systems

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Reconfigurable data processing using duplex fault tolerance system

Reconfigurable data processing using duplex fault tolerance ...

引用

international conference on Innovations in Information,embedded and Communication systems (ICIIECS)

作者： M. Shobana Murugan.S Senthil Valliammai Engineering college Anna University India Valliammai Engineering college Anna University Chennai India

Many digital signal processor designers and manufacturers are facing one big challenge, that is, how to perform complex mathematical function calculations more efficiently. To gain efficiency, it is needed to dig inside our complete designing cycle which contains algorithms, architectures, hardware technology, power supply etc. Fast Fourier Transform (FFT) is widely used transform in digital applications especially in communication systems. An FFT is an important processing block in these systems, which takes most of the hardware complexity in a digital baseband transceiver for instance. Half duplex is one of the redundancy based architecture. The duplex fault tolerance system is used to detect and localization of faulty module which leads to reconfigure the faulty module. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against single even upsets (SEUs). In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.

关键词： Field programmable gate arrays Algorithm design and analysis Discrete Fourier transforms Multiplexing computer architecture

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Design verification based on Hardware-In-the-Loop simulation for photovoltaic system

Design verification based on Hardware-In-the-Loop simulation...

引用

IEEE SSD international Multi-conference on systems, Signals and Devices

作者： Hanen Abbes Mossaad Ben Ayed Hafedh Abid Mohamed Abid Department of Electrical Engineering University of Sfax Sfax Tunisia Department of Electrical Engineering Laboratory of Sciences and techniques of Automatic control & computer engineering (Lab-STA) Universite de Sfax Sfax TN

Due to the increasing complexity of photovoltaic systems and problems linked to development and design, verification of the entire system operation is essential before real implementation. Besides, high requirements of a real-time simulation and control circuit prototyping before application increases safeness, and can reduce time and costs of implementation. For this end, the purpose of this work is to achieve photovoltaic system development and its design verification through system simulation using FPGA device. The verification method used in this study is the “Hardware-In-the-Loop” (HIL) simulation method. It provides an effective platform for developing and testing real time embedded systems. In this paper, we design the power circuit and we develop the open-circuit voltage controller which tracks the maximum power point. Then, the HIL simulation process is performed for the photovoltaic system. The efficiency of the photovoltaic system is validated by the simulation results.

关键词： Photovoltaic systems Mathematical model Field programmable gate arrays Integrated circuit modeling Digital signal processing Computational modeling

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Architectural Low-Power Design Using Transaction-Based System modeling and simulation 14

Architectural Low-Power Design Using Transaction-Based Syste...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mischkalla, Fabian Mueller, Wolfgang Univ Paderborn C LAB D-33102 Paderborn Germany

ISBN: (纸本)9781479937707

Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.

关键词： SystemC/TLM IEEE 1801-2013 (UPF) Power Intent simulation & Validation

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Current challenges in simulations of HPC systems

Current challenges in simulations of HPC systems

引用

international conference on High Performance Computing & simulation (HPCS)

作者： Salvador Petit Department of Computer Engineering Universitat Politècnica de València València Spain

simulation of many-core HPC systems is nowadays an active and fruitful area of research. Recent and future proposals are driven by the need of a fast, efficient, and comprehensive simulation framework. This simulation framework should be complete in several ways. First, it should model a wide range of components and provide the mechanisms necessary to plug-in more components as needed. Second, it should allow the designer to focus on critical components while avoiding a large part of the simulation complexity. Each of these components should be able to be evaluated with multiple models with distinct detail levels, ranging from simply analytical models to detailed cycle-accurate simulations. Third, a complete simulation framework should provide a wide range of metrics of interest for the designer and the market. Finally, support for heterogeneous architectures combining CPU and GPU, as well as some degree of reconfigurability is surely required. Building such titanic framework is and will be a collaborative process between researchers around the globe and it is expected to be a hot research topic for the next years.

关键词： Computational modeling Multicore processing Synchronization computers Accuracy Complexity theory

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Evaluation of Message Passing Synchronization Algorithms in embedded systems 14

Evaluation of Message Passing Synchronization Algorithms in ...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Papadopoulos, Lazaros Walulya, Ivan Tsigas, Philippas Soudris, Dimitrios Barry, Brendan Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece Chalmers Comp Sci & Engn S-41296 Gothenburg Sweden Movidius Ltd Dublin Ireland

ISBN: (纸本)9781479937707

The constantly increasing computational power of the embedded systems is based on the integration of a large number of cores on a single chip. In such complex platforms, the synchronization of the accesses of the shared memory data is becoming a major issue, since it affects the performance of the whole system. This problem, which is currently a challenge in the embedded systems, has been studied in the High Performance Computing domain, where several message passing algorithms have been designed to efficiently avoid the limitations coming from locking. In this work, inspired from the work on message passing synchronization algorithms in the High Performance Computing domain we design and evaluate a set of synchronization algorithms for multi-core embedded platforms. We compare them with the corresponding lock-based implementations and prove that message passing synchronization algorithms can be efficiently utilized in multi-core embedded systems. By using message passing synchronization instead of lock-based, we managed to reduce the execution time of our benchmark up to 29.6%.

关键词： message passing multi-core embedded systems lock-free

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On Tokens and Signals: Bridging the Semantic Gap between Dataflow Models and Hardware Implementations 14

On Tokens and Signals: Bridging the Semantic Gap between Dat...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Tripakis, Stavros Limaye, Rhishikesh Ravindran, Kaushik Wang, Guoqiang Univ Calif Berkeley Berkeley CA 94720 USA Aalto Univ Espoo Finland Natl Instruments Corp Berkeley CA USA

ISBN: (纸本)9781479937707

Dataflow models serve as useful abstractions of digital hardware in signal processing and other application domains. But when can one say that a certain dataflow model faithfully captures a given piece of hardware? To answer this question we develop a formal conformance relation between the heterogeneous formalisms of (1) finite state machines with synchronous semantics, used to model hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.

关键词： data flow token computer hardware signals Semantics Queue signal processing

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Highly-Parallel Special-Purpose Multicore Architecture for SystemC/TLM simulations 14

Highly-Parallel Special-Purpose Multicore Architecture for S...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ventroux, N. Peeters, J. Sassolas, T. Hoe, James C. CEA LIST Embedded Comp Lab F-91191 Gif Sur Yvette France Carnegie Mellon Univ Comp Architecture Lab CALCM Pittsburgh PA 15213 USA

ISBN: (纸本)9781479937707

The complexity of SystemC virtual prototyping is continuously increasing. Accelerating RTL/TLM SystemC simulations is essential to control future SoC development cost and time-to-market. In this paper, we present RAVES, a highly-parallel special-purpose multicore architecture that achieves simulation performance more efficiently by parallel execution of light-weight user-level threads on many small cores. We present a design study based on the virtual prototype of RAVES processors running a co-designed custom SystemC kernel. Our evaluation suggests that a 64-core RAVES processor can deliver up to 4.47x more simulation performance than a high-end x86 processor.

关键词： Virtual prototyping Multi-core processors parallel execution PROCESSOR simulating ARCHITECTURE Building construction

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