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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2832 条记录，以下是751-760 订阅

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Research on Campus Mobile Model Based on Periodic Purpose for Opportunistic Network

Research on Campus Mobile Model Based on Periodic Purpose fo...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Xin He Chunxi Wang Tianxu Liu Keke Gai Dehong Chen Lin Bai College of Software and College of Environment and Planning Henan University Kaifeng Henan Graduate School Henan University Kaifeng Henan College of Computer and Information Engineering Henan University Kaifeng Henan Department of Computer Science Pace University New York NY USA

In the study of opportunistic network, the design of mobile model directly affects the architecture of opportunistic network and the efficiency of routing algorithm. On the discussion of human movement characteristics, this paper analyzed the characteristics of students' movement in campus environment and presented a campus mobile model based on periodic purpose, Periodical-Purpose Campus Mobility Model (PPCMM). The campus scene was divided into five regions. Nodes choose destination location through objective probability. The number of nodes was counted in different regions and different time. The simulation results show that the model reflects the purposiveness and periodicity of the students' movement and it is in accord with the actual students' movement.

关键词： Mobile communication Mobile computing Analytical models Computational modeling Trajectory embedded systems Data models

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A study of networking software induced latency

A study of networking software induced latency

引用

international conference and Workshops on Networked systems (NetSys)

作者： Alexander Beifuß Daniel Raumer Paul Emmerich Torsten M. Runge Florian Wohlfart Bernd E. Wolfìnger Georg Carle Universität Hamburg Department of Computer Science Telecommunications and Computer Networks Department of Computer Science Network Architectures and Services Technische Universität München Department of Computer Science Telecommunications and Computer Networks Universität Hamburg

For long time, high-speed packet processing has been reserved for specialized hardware devices since software based solutions were not able to achieve the required performance. However, off-the-shelf packet processing hardware and software improved over the last years, which is why software based solutions cope with high-speed traffic nowadays. Due to the flexibility of software there is a trend towards doing packet processing in software, e.g. using OpenFlow or virtual switches. Although packet processing in software offers many capabilities, the complexity of such software bases solutions makes it hard to evaluate, optimize, or predict the networking performance of servers, end user hosts, or routers. We present a study that investigates the packet latency caused by the packet processing in the Linux network stack. We develop a simulation model in ns-3 for packet processing via the Linux network stack that helps understanding of its performance implications. We validate our simulation model based on measurements with nanosecond accuracy and software profiling.

关键词： Hardware Linux Kernel Throughput Software measurement Load modeling

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Game Based Resource Allocation Scheme for Dynamic Environments

Game Based Resource Allocation Scheme for Dynamic Environmen...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Youngjae Park Sungwook Kim Computer science and engineering Sogang University Seoul South Korea

ISBN: (纸本)9781479989386

In this paper, we propose a new strategic security resource allocation scheme based on the Blotto game. In the Blotto game, players are tasked to simultaneously distribute limited resources over several objects. For the efficient security resource allocation, the proposed game model constitutes a class of repeated two-person game while employing the iterative learning approach to approximate an optimal solution. A simulation shows that our proposed scheme can effectively respond the current conditions and obtain better performance than other existing scheme under dynamically changeable environments.

关键词： Security Games Resource management Information systems Computational modeling Dynamic scheduling Iterative methods

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A Comprehensive ASIC/FPGA Prototyping Environment for Exploring embedded Processing systems for Advanced Driver Assistance Applications 14

A Comprehensive ASIC/FPGA Prototyping Environment for Explor...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Giesemann, Florian Paya-Vaya, Guillermo Blume, Holger Limmer, Matthias Ritter, Werner Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Daimler AG Vis Enhancement D-89081 Ulm Germany

ISBN: (纸本)9781479937707

The development of complex algorithms for advanced driver assistance systems is a challenging task, due to the high innovation rate and processing demands of applications in this field. The development is usually supported by a software development framework that provides an infrastructure (e.g., access to sensor data) that simulates and evaluates the algorithms. One problem, especially with computationally intensive algorithms, is the slow simulation speed. This paper presents a prototyping environment that connects a software development framework with a FPGA-based hardware platform. This allows implementing computationally intensive tasks in hardware. The proposed rapid prototyping system not only reduces the simulation time, thereby allowing the software designer to evaluate algorithmic parameters with quicker feedback, but also allows verifying and evaluating hardware modules for rapid prototyping. A case study is presented in which a traffic sign detection algorithm is implemented on a soft-core processor. By using the hardware implementation the simulation was accelerated by a factor of 65, compared to the pure software implementation.

关键词： rapid prototyping FPGA design space exploration hardware-software-co-simulation

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Micro-architectural simulation of In-order and Out-of-order ARM Microprocessors with gem5 14

Micro-architectural Simulation of In-order and Out-of-order ...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Endo, Fernando A. Courousse, Damien Charles, Henri-Pierre CEA LIST Dept Architecture Concept & Logiciels Embarques F-38054 Grenoble France

ISBN: (纸本)9781479937707

Heterogeneous multicore systems have gained momentum, specially for embedded applications, thanks to the performance and energy consumption trade-offs provided by in-order and out-of-order cores. Micro-architectural simulation models the behavior of pipeline structures and caches with configurable parameters. This level of abstraction is well known for being flexible enough to quickly evaluate the performance of new hardware implementations, such as future heterogeneous multicore platforms. However, currently, there is no open-source micro-architectural simulator supporting both in-order and out-of-order ARM cores. This article describes the implementation and accuracy evaluation of a micro-architectural simulator of Cortex-A cores, supporting in-order and out-of-order pipelines and based on the open-source gem5 simulator. We explain how to simulate Cortex-A8 and Cortex-A9 cores in gem5, and compare the execution time of ten benchmarks with real hardware. Both models, with average absolute errors of only 7 %, are more accurate than similar micro-architectural simulators, which show average absolute errors greater than 15 %.

关键词： embedded systems

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Using ArchC to model a Hard-PLC processor

Using ArchC to model a Hard-PLC processor

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international conference on Industrial Instrumentation and Control (ICIC)

作者： Johannes Kohl Dietmar Fey Jürgen Bäsig Chair of Computer Science 3 University of Erlangen-Nürnberg Erlangen Germany Department Electrical Engineering Precision Engineering Information Technology Technische Hochschule Nürnberg Nürnberg Germany

The advancing automation of the industrial production requires faster and more efficient programmable logic controllers. Today's controller architectures based on specialized processors to execute the STL application are at their limits. For any further improvement the architecture of these processors needs to evolve from single core in order execution to a multicore out of order architecture. This step can not occur without additions to the PLC's instruction set. Therefore a PLC processor instruction set simulation is required that allows a quick evaluation of the effectiveness and efficiency of instruction set changes as well as changes to the processor's architecture. Current architecture description languages (ADL) allow the fast modeling of these changes with enough flexibility for the planned improvements and provide fast simulation speed. This work presents for the first time an instruction set simulation environment for STL compatible PLC processors using the ADL ArchC as a base for further research.

关键词： Registers Object oriented modeling Process control Operating systems Multicore processing Memory management

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Definition of an embedded Driver Model for Driving Behavior Prediction within the DESERVE Platform 14

Definition of an Embedded Driver Model for Driving Behavior ...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Klimke, Jens Themann, Philipp Klas, Christoph Eckstein, Lutz Rhein Westfal TH Aachen Inst Kraftfahrzeuge Ika Adv Driver Assistance Syst D-52074 Aachen Germany

ISBN: (纸本)9781479937707

The use of driver models within advanced driver assistance systems (ADAS) allows anticipating the driving behavior of the vehicle and all traffic participants in the close vicinity. This valuable information could considerably improve the performance as well as the acceptance of ADAS. Consequently complex driver models need to be integrated in embedded systems. This work, first of all, aims to summarize important driver models described in literature. Based upon this a suitable approach to implement a driver model on an embedded system is derived. The model used, focuses on the longitudinal driving and lane change behavior of drivers. The system architecture is derived and optimized for real-time execution. The driver model is analyzed in detailed simulations. Test drives in a small scale naturalistic driving study are used to validate the driver model. This paper defines a standard driver model to be implemented as part of the DESERVE platform within the Artemis project "DESERVE". As embedded automotive hardware the dSpace MicroAutoBox II is used. The paper summarizes approaches and examples to use the generated prediction data in ADAS like ACC.

关键词： Advanced driver assistance systems

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Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform

Job-Arrival Aware Distributed Run-Time Resource Management o...

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IEEE/IFIP international conference on embedded and Ubiquitous Computing, EUC

作者： Vasileios Tsoutsouras Sotirios Xydis Dimitrios Soudris School of Electrical and Computer Engineering National Tech. Univ. of Athens Greece

Modern computing systems are dealing with a diverse set of complex and dynamic workloads in the presence of varying job arrival rates. This diversity is raising the need for the development of sophisticated run-time mechanisms that efficiently manage system's resources. In addition, moving towards kilo-core processor architectures, centralized resource management approaches will most probably form a severe performance bottleneck, thus the study of Distributed Run-Time Resource Management (DRTRM) schemes is now gaining a lot of attention. In this paper, we propose a job-arrival aware DRTRM framework for applications with malleable characteristics, implemented on top of the Intel Single-Chip Cloud computer (SCC) many-core platform. We show that resource allocation is highly affected not only by the internal decision mechanisms but also from the incoming application interval rate on the system. Based on this observation, we propose an effective admission control strategy utilizing Voltage and Frequency Scaling (VFS) of parts of the DRTRM which eventually retains the distributed decision making thus improving system performance in combination with significant gains in its consumed energy.

关键词： Resource management Voltage control computers Admission control Reliability Dynamic scheduling Computational modeling

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Efficient prediction of short term load using Chebyshev functional link artificial neural network

Efficient prediction of short term load using Chebyshev func...

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international conference on Innovations in Information,embedded and Communication systems (ICIIECS)

作者： Arjun Baliyan Mishra Sudhansu Kumar Department of EEE BIT Mesra Jharkhand India Birla Institute of Technology Ranchi Jharkhand IN

In this paper, we have presented an efficient single layer ANN structure called functional link ANN (FLANN) for the prediction of short time load demand. In contrast to a feed forward ANN structure, i.e. a multilayer perceptron (MLP), the FLANN is basically a single layer structure in which non-linearity is introduced by enhancing the input pattern with nonlinear function expansion. In FLANN structure the need of a hidden layer is eliminated and it requires much less computation than that of MLP. In this paper three different functional expansions have been applied. From the simulation studies, it is clear that with the Chebyshev functional expansion, the FLANN network performs best among other competing networks for this challenging and interesting problem. Performance comparisons of the all the networks were carried out through extensive computer simulations.

关键词： Artificial neural networks Load modeling Chebyshev approximation Load forecasting Training Computational complexity

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Modana: An Integrated Framework for modeling and Analysis of Energy-Aware CPSs

Modana: An Integrated Framework for Modeling and Analysis of...

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IEEE Annual international computer Software and Applications conference (COMPSAC)

作者： Bei Cheng Xiao Wang Jufu Liu Dehui Du Shanghai Key Laboratory of Trustworthy Computing East China Normal University Shanghai China

Cyber-Physical systems (CPSs) as advanced embedded systems integrating computation with physical process are increasingly penetrating into our life. modeling and analysis for such systems closely involved with us are actively researched. A current challenging problem is how to take advantages of existing technologies like SysML/MARTE, Modelica and Statistical Model Checking (SMC) through effective integration. Moreover, the lack of efficient methodologies or tools for modeling and analysis of CPSs makes the gap between design and analysis models hard to bridge. To solve these problems, we present a framework named Modana to achieve an integrated process from modeling with SysML/MARTE to analysis with SMC for CPSs in terms of Non Functional Properties (NFP) such as time, energy, etc. Functional Mock-up Interface (FMI), as a connecting link between modeling and analysis, plays a major role in coordinating various tools for co-simulation to generate traces as the input of statistical model checker. To demonstrate the capability of Modana framework, we model energy-aware buildings as a case study, and discuss the analysis on energy consumption in different scenarios.

关键词： Unified modeling language Analytical models Object oriented modeling Mathematical model Stochastic processes Libraries Computational modeling

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