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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Pre-architectural Performance Estimation for ASIP Design Based on Abstract Processor Models 14

Pre-architectural Performance Estimation for ASIP Design Bas...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Eusse, Juan Fernando Williams, Christopher Murillo, Luis Gabriel Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany

ISBN: (纸本)9781479937707

Application Specific Instruction Set Processors (ASIPs) seek for an optimal performance/area/energy trade-off for a given algorithm. In all current design methodologies an architectural model must be first manually created based on designers experience. These models are increasingly refined until the design constraints are met, through several time consuming algorithmic/architecture co-exploration iterations. This paper presents a novel performance estimation approach that shortens the design cycle of existing methodologies by providing an early assessment of the impact of customizations on the achievable performance. The approach does so by eliminating the need for a completely specified architecture, without limiting designer's freedom and without simulating the application repeatedly. Overall, our approach reduces the number of necessary co-exploration iterations, thus increasing design productivity. We validate our approach via two different case studies: a butterfly-enabled ASIP for Fast Fourier Transform computation and a Connected Components Labeling ASIP for computer vision.

关键词： Performance Evaluation ASIP gene design constraints connected component Design flow Customization Designers PROCESSOR images computer vision iterative methods

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Variable Length Instruction Compression on Transport Triggered architectures 14

Variable Length Instruction Compression on Transport Trigger...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Helkala, Janne Viitanen, Timo Kultala, Heikki Jaaskelainen, Pekka Takala, Jarmo Zetterman, Tommi Berg, Heikki Tampere Univ Technol Dept Pervas Comp FIN-33101 Tampere Finland Nokia Res Ctr Radio Syst Lab Espoo Finland

ISBN: (纸本)9781479937707

The SRAM memories used for embedded microprocessor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.

关键词： code compression instruction memory variable length Power dissipation DECODING instruction fetch instruction low power consumption compression ARCHITECTURE PROCESSOR

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Development and Design of a Platform for Arbitration and Sharing Control Applications -a DESERVE approach- 14

Development and Design of a Platform for Arbitration and Sha...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perez, Joshue Gonzalez, David Nashashibi, Fawzi Tango, Fabio Pallaro, Nereo Dunand, Gwenael Rolfsmeier, Andre INRIA Le Chesnay France Ctr Ric FIAT Orbassano Italy Intempora Issy Les Moulineaux France dSpace Paderborn Germany

ISBN: (纸本)9781479937707

In this paper, a description of the ADAS development platform in DESERVE project framework is presented. This work is framed within the Sub Project 2 (Development platform) of DESERVE project, and it is divided in 6 different and complementary lines of work. Most of the functions described in the tools and development systems, perception layer and the platform system architecture show the modularity and scalability of our proposal. Moreover, based on vehicle modelling, driver behaviour and intention, a first approach for arbitration and control strategies, which can anticipate the priorities on the control in emergency situations, is described. Furthermore, some simulations will allow the virtual testing for the future implementation in demonstrators. The presented work is the core of DESERVE project, and it is developed in parallel with Driver behaviour and HMI activities (SP3). This work presents some of the achievements in SP2, mainly the application platform integration in one of the demonstrators, along with the arbitration and sharing control, based on intelligent techniques (Fuzzy logic). simulation shows the feasibility of proposal. This approach will be tested, integrated and validated in a real vehicle in the next stages of the project.

关键词： ADAS embedded systems Arbitration Control Virtual testing modelling

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GPGPU Workload Characteristics and Performance Analysis 14

GPGPU Workload Characteristics and Performance Analysis

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Lal, Sohan Lucas, Jan Andersch, Michael Alvarez-Mesa, Mauricio Elhossini, Ahmed Juurlink, Ben TU Berlin Embedded Syst Architecture D-10587 Berlin Germany

ISBN: (纸本)9781479937707

GPUs are much more power-efficient devices compared to CPUs, but due to several performance bottlenecks, the performance per watt of GPUs is often much lower than what could be achieved theoretically. To sustain and continue high performance computing growth, new architectural and application techniques are required to create power-efficient computing systems. To find such techniques, however, it is necessary to study the power consumption at a detailed level and understand the bottlenecks which cause low performance. Therefore, in this paper, we study GPU power consumption at component level and investigate the bottlenecks that cause low performance and low energy efficiency. We divide the low performance kernels into low occupancy and full occupancy categories. For the low occupancy category, we study if increasing the occupancy helps in increasing performance and energy efficiency. For the full occupancy category, we investigate if these kernels are limited by memory bandwidth, coalescing efficiency, or SIMD utilization.

关键词： Traffic Bottlenecks Energy efficiency Vehicle Occupancy Power consumption Energy units memory bandwidth central processing units Seeds performance characteristics Kernel Workload

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FAUPU - A design framework for the development of programmable image processing architectures

FAUPU - A design framework for the development of programmab...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Marc Reichenbach Tobias Lieske Steffen Vaas Konrad Haublein Dietmar Fey Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE

The development of fast image processing architectures in smart camera systems is a very important task. Nowadays, many applications, such as robot control or advanced driver assistance systems, require fast image acquisition and processing utilizing embedded devices. These requirements have lead to specialized hardware architectures for image processing. However, an overall approach to designing an optimal image processing architecture, remains unsolved. In most cases the architectures are application-specific, which results in high throughput, but they are also mostly limited to one single task. Other solutions use high performance DSPs which are very flexible but lack in performance and/or power consumption compared to the application-specific implementation. Hence, we designed a framework, called FAUPU1 (FAU Processing Unit), which can generate an architecture for a specific range of image processing applications and furthermore is able to yield real-time and power constraints. As a result, a field of programmable processing elements (PE) is instantiated. The fields structure and size is highly generic in terms of the given requirements (e.g. available hardware resource, timing constraints). The architecture of the PE is generic as well and strongly depends on the requisite types and amount of image processing operations. Due to optimized data access and a strong usage of parallel processing, real-time execution of complex image processing operations is possible. In addition to an executable simulation in SystemC our framework is able to generate the resulting architecture in synthesizable VHDL code, which can be implemented on arbitrary FPGA platforms as well as integrated circuit (IC) designs.

关键词： computer architecture Image processing Hardware Algorithm design and analysis Field programmable gate arrays Smart cameras

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SiNUCA: A Validated Micro-Architecture Simulator

SiNUCA: A Validated Micro-Architecture Simulator

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Marco Antonio Zanata Alves Carlos Villavieja Matthias Diener Francis Birck Moreira Philippe Olivier Alexandre Navaux Universidade Federal do Rio Grande do Sul Porto Alegre RS BR Informatics Institute - Federal University of Rio Grande do SuI Google

In order to observe and understand the architectural behavior of applications and evaluate new techniques, computer architects often use simulation tools. Several cycle-accurate simulators have been proposed to simulate the operation of the processor on the micro-architectural level. However, an important step before adopting a simulator is its validation, in order to determine how accurate the simulator is compared to a real machine. This validation step is often neglected with the argument that only the industry possesses the implementation details of the architectural components. The lack of publicly available micro-benchmarks that are capable of providing insights about the processor implementation is another barrier. In this paper, we present the validation of a new cycle-accurate, trace-driven simulator, SiNUCA. To perform the validation, we introduce a new set of micro-benchmarks to evaluate the performance of architectural components. SiNUCA provides a controlled environment to simulate the micro-architecture inside the cores, the cache memory sub-system with multi-banked caches, a NoC interconnection and a detailed memory controller. Using our micro-benchmarks, we present a simulation validation comparing the performance of real Core 2 Duo and Sandy-Bridge processors, achieving an average performance error of less than 9%.

关键词： computer architecture Computational modeling Routing Benchmark testing Cache memory Random access memory Process control

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Scalable scheduling of energy control systems

Scalable scheduling of energy control systems

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Proceedings of the international conference on embedded Software (EMSOFT)

作者： Truong X. Nghiem Rahul Mangharam Ecole Polytechnique Federale de Lausanne Lausanne VD CH University of Pennsylvania Philadelphia PA US

Peak power consumption is a universal problem across energy control systems in electrical grids, buildings, and industrial automation where the uncoordinated operation of multiple controllers result in temporally correlated electricity demand surges (or peaks). While there exist several diferent approaches to balance power consumption by load shifting and load shedding, they operate on coarse grained time scales and do not help in de-correlating energy sinks. The Energy System Scheduling Problem is particularly hard due to its binary control variables. Its complexity grows exponentially with the scale of the system, making it impossible to handle systems with more than a few variables. We developed a scalable approach for fine-grained scheduling of energy control systems that novelly combines techniques from control theory and computer science. The original system with binary control variables are approximated by an averaged system whose inputs are the utilization values of the binary inputs within a given period. The error between the two systems can be bounded, which allows us to derive a safety constraint for the averaged system so that the original system's safety is guaranteed. To further reduce the complexity of the scheduling problem, we abstract the averaged system by a simple single-state single-input dynamical system whose control input is the upper-bound of the total demand of the system. This model abstraction is achieved by extending the concept of simulation relations between transition systems to allow for input constraints between the systems. We developed conditions to test for simulation relations as well as algorithms to compute such a model abstraction. As a consequence, we only need to solve a small linear program to compute an optimal bound of the total demand. The total demand is then broken down, by solving a linear program much smaller than the original program, to individual utilization values of the subsystems, whose actual schedule is the

关键词： Computational modeling Optimization Safety Complexity theory Schedules Heating

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Characterizing communication behavior of dataflow programs using trace analysis 14

Characterizing communication behavior of dataflow programs u...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Janneck, Jorn W. Casale Brunet, Simone Mattavelli, Marco Department of Computer Science Lund University Sweden EPFL SCI STI MM Ecole Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9781479937707

This paper investigates the relationship between two ways of analyzing streaming systems: trace analysis for dataflow programs with firing, and network calculus for network flows. While the former focuses on the structure of the dataflow computation while idealizing the interaction with the environment, the latter characterizes the temporal properties of flows of data, largely abstracting from the computations that connect them. In this work, we show how a trace analysis can be used to derive a description of communication behavior of a dataflow program in terms of network calculus, which is then applied to answering a question about the buffer sizing. The example being studied is an MPEG-4 video decoder. © 2014 IEEE.

关键词： Calculations

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Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs

Exploration of Migration and Replacement Policies for Dynami...

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international conference on VLSI Design

作者： Shirshendu Das Hemangee K. Kapoor Department of CSE Indian Institute of Technology Guwahati Assam India

Multicore processors have proliferated several domains ranging from small scale embedded systems to large data-centers, making tiled CMPs (TCMP) the essential next generation scalable architecture. More processors need proportionally large cache to support the concurrent applications. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (SNUCA) has a fixed address mapping policy whereas dynamic NUCA (DNUCA) allows blocks to relocate nearer to the processing cores at runtime. The DNUCA architectures are well explored for systems with centralized cache banks and having processors along the periphery. SNUCA is well understood and explored for tiled CMPs whereas the same is not the case for DNUCA. Towards exploring various implementations of DNUCA for tiled CMPs, this paper presents an architecture along with migration and replacement policies for tiled CMPs. Experimental results show improvements with respect to TCMP based SNUCA. We discuss the differences and challenges of TCMP based DNUCA compared to original DNUCA, and present results for different configurations of migration and replacement policies. simulation results shows improvements over TCMP based SNUCA by 44.7% and 9.6% in terms of miss-rate and cycles per instruction (CPI) respectively.

关键词： Benchmark testing Program processors computer architecture Power system faults Power system protection System-on-chip Very large scale integration

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CMT-bone: A Mini-App for Compressible Multiphase Turbulence simulation Software

CMT-bone: A Mini-App for Compressible Multiphase Turbulence ...

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IEEE international conference on Cluster Computing

作者： Nalini Kumar Mrugesh Sringarpure Tania Banerjee Jason Hackl S. Balachandar Herman Lam Alan George Sanjay Ranka Department of Electrical and Computer Engineering Department of Mechanical and Aerospace Engineering Department of Computer Information Science and Engineering University of Florida Gainesville FL

Designed with the goal of mimicking key features of real HPC workloads, mini-apps have become an important tool for co-design. An investigation of mini-app behavior can provide system designers with insight into the impact of architectures, programming models, and tools on application performance. Mini-apps can also serve as a platform for fast algorithm design space exploration, allowing the application developers to evaluate their design choices before significantly redesigning the application codes. Consequently, it is prudent to develop a mini-app alongside the full blown application it is intended to represent. In this paper, we present CMT-bone a mini-app for the compressible multiphase turbulence (CMT) application, CMT-nek, being developed to extend the physics of the CESAR Nek5000 application code. CMT-bone consists of the most computationally intensive kernels of CMT-nek and the communication operations involved in nearest-neighbor updates and vector reductions. The mini-app represents CMT-nek in its most mature state and going forward it will be developed in parallel with the CMT-nek application to keep pace with key new performance impacting changes. We describe these kernels and discuss the role that CMT-bone has played in enabling interdisciplinary collaboration by allowing application developers to work with computer scientists on performance optimization on current architectures and performance analysis on notional future systems.

关键词： computer architecture Computational modeling Kernel Mathematical model computers Optimization

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