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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是71-80 订阅

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A New State Model for DRAMs Using Petri Nets 17

A New State Model for DRAMs Using Petri Nets

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jung, Matthias Kraft, Kira Wehn, Norbert Fraunhofer IESE D-67663 Kaiserslautern Germany Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)9781538634370

The functionality of DRAMs, especially the state transitions are described in JEDEC standards. These standards contain a finite state machine, which intends to provide an overview of the possible state transitions and the commands to control them. However, today's DRAMs are highly concurrent devices as they provide bank parallelism. The state diagram used in JEDEC standards does not model this concurrency and furthermore it is misleading in several aspects. In this paper, for the first time we present an easily comprehensive model of the DRAM states and transitions, using a Petri Net, which covers also the DRAM concurrency.

关键词： Random access memory Petri nets Inhibitors Standards Parallel processing computer architecture Concurrent computing Petri nets random access machine computer Architecture PARALLEL PROCESSING (computerS) Parallel programming DRAM1 gene Inhibitors Joint Electron Device Engineering Council State Change finite state machines

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System simulation with gem5 and SystemC The Keystone for Full Interoperability 17

System Simulation with gem5 and SystemC The Keystone for Ful...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Menard, Christian Castrillon, Jeronimo Jung, Matthias Wehn, Norbert Tech Univ Dresden Dresden Germany Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781538634370

SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.

关键词： Time-varying systems Time-domain analysis Couplings Timing Protocols Hardware Industries Time domain analysis Couplings time-varying systems computer hardware execution time systems simulation protocols industries coupling Interoperability Space Exploration keystone

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Static energy saving through multi-bank memory architecture

Static energy saving through multi-bank memory architecture

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Lafond, Sebastien Lilius, Johan Turku Ctr Comp Sci Embedded Syst Lab Lemminkaisenkatu 14A FIN-20520 Turku Finland Abo Akad Univ Dept Informat Technol FIN-20520 Turku Finland

ISBN: (纸本)1424401550

Managing the energy consumption of embedded systems has become a major problem with the increasing demand for portable electronic devices. This paper propose a multi-bank memory architecture as a solution to decrease the static energy cost in memory. We set up the equations ruling the optimization problem for decreasing the memory static energy cost, analyze the impact of different parameters on the energy cost and finally present some case study results.

关键词： Memory architecture

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Can a reconfigurable architecture beat ASIC as a CNN accelerator? 17

Can a reconfigurable architecture beat ASIC as a CNN acceler...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jafri, Syed M. A. H. Hemani, Ahmed Stathis, Dimmitrios Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538634370

To exploit the high accuracy, inherent redundancy, and embarrassingly parallel nature of Convolutional Neural Networks (CNN), for intelligent embedded systems, many dedicated CNN accelerators have been presented. These accelerators are optimized to employ compression, tiling, and layer merging for a specific data flow/parallelism pattern. However, the dimension of a CNN differ widely from one application to another (and also from one layer to another). Therefore, the optimal parallelism and data flow pattern also differs significantly in different CNN layers. An efficient accelerator should have flexibility to not only efficiently support different data flow patterns but also to interleave and cascade them. To achieve this ability requires configuration overheads. This paper analyzes whether the reconfiguration overheads for interleaving and cascading multiple data flow and parallelism patterns are justified. To answer this question, we first design a reconfigurable CNN accelerator, called ReCon. ReCon is the compared with state-of-the-art accelerators. Post-layout synthesis results reveal that ReCon provides up to 2.2X higher throughput and up to 2.3X better energy efficiency at the cost of 26-35% additional area.

关键词： Kernel Parallel processing Random access memory Convolution Merging Feature extraction computer architecture random access machine merger computer Architecture PARALLEL PROCESSING (computerS) Convolution data flow Feature extraction Kernel Accelerators Reconfigurable architectures one layer

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Task Graph Mapping and Scheduling on Heterogeneous architectures Under Communication Constraints 17

Task Graph Mapping and Scheduling on Heterogeneous Architect...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Emeretlis, A. Tsakoulis, T. Theodoridis, G. Alefragis, P. Voros, N. Univ Patras Dept Elect & Comp Engn Patras Greece TEI Western Greece Dept Comp Informat Engn Antirio Greece

ISBN: (纸本)9781538634370

An approach for mapping applications represented as Directed Acyclic Graphs (DAGs) on platforms consisting of heterogeneous cores considering the communication overhead between the cores is introduced. The approach is based on the Benders decomposition principle and integrates Integer Linear and Constraint Programming formulations. Both formulations take into account the communication delay between dependent tasks that are assigned to different cores trying to optimize the application's execution time. The proposed approach succeeds to provide the optimal solution in all cases of synthetic and real-application DAGs, while the pure ILP model fails more than half of them. Also, the average solution time of the proposed method is about 1 minute, whereas for instances solved by both models, the speedup equals to 11x over the ILP model.

关键词： Multicore processing Processor scheduling Integer linear programming Constraint programming

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Bridging the Semantic Gap Between Heterogeneous modeling Formalisms and FMI 15

Bridging the Semantic Gap Between Heterogeneous Modeling For...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Tripakis, Stavros Aalto Univ Espoo Finland Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781467373111

FMI (Functional Mockup Interface) is a standard for exchanging and co-simulating model components (called FMUs) coming from potentially different modeling formalisms, languages, and tools. Previous work has proposed a formal model for the co-simulation part of the FMI standard, and also presented two co-simulation algorithms which can be proven to have desirable properties, such as determinacy, provided the FMUs satisfy a formal contract. In this paper we discuss the principles for encoding different modeling formalisms, including state machines (both untimed and timed), discrete-event systems, and synchronous dataflow, as FMUs. The challenge is to bridge the various semantic gaps (untimed vs. timed, signals vs. events, etc.) that arise because of the heterogeneity between these modeling formalisms and the FMI API.

关键词： PTPRU gene discrete event systems state machines deterministic modeling Semantics

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Application Autotuning to Support Runtime Adaptivity in Multicore architectures 15

Application Autotuning to Support Runtime Adaptivity in Mult...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Gadioli, Davide Palermo, Gianluca Silvano, Cristina Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781467373111

In this work, we introduce an application auto-tuning framework to dynamically adapt applications in multicore architectures. In particular, the framework exploits design-time knowledge and multi-objective requirements expressed by the user, to drive the autotuning process at the runtime. It also exploits a monitoring infrastructure to get runtime feed-back and to adapt to external changing conditions. The intrusiveness of the autotuning framework in the application (in terms of refactoring and lines of code to be added) has been kept limited, also to minimize the integration cost. To assess the proposed framework, we carried out an experimental campaign to evaluate the overhead, the relevance of the described features and the efficiency of the framework.

关键词： Self tuning Runtime Frameworks lines of code Multi-core processors ARCHITECTURE

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Parallel SystemC simulation for ESL Design using Flexible Time Decoupling 15

Parallel SystemC Simulation for ESL Design using Flexible Ti...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Weinstock, Jan Henrik Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany

ISBN: (纸本)9781467373111

Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4x on a quad-core host.

关键词： simulator simulating English as Second Language Platform design tools Parallel Lines Speeding Engineers design process DECOUPLING Advance Time

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An IP core for embedded Java systems

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Uhrig, Sascha Mische, Joerg Ungerer, Theo Univ Augsburg Inst Comp Sci D-86159 Augsburg Germany

ISBN: (纸本)9783540736226

This paper proposes a multithreaded Java processor as an IP core for Altera's System-on-Programmable-Chip environment. The processor core is an enhancement of the earlier developed multithreaded Java processor named Komodo. It features a real-time capable garbage collection and integrated real-time scheduling schemes. Hence, it is suitable for embedded hard, soft, and non real-time systems. The facts that the processor is designed as an IP core and that it is a special Java processor makes both easier: hardware design and software development.

关键词： implantable systems embedded system-on-a-chip implementations multithreaded processors embedded operating systems real-time embedded systems Java processor

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Just-in-Time Verification in ADL-based Processor Design

Just-in-Time Verification in ADL-based Processor Design

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Auras, Dominik Minwegen, Andreas Deidersen, Uwe Schuermans, Stefan Ascheid, Gerd Leupers, Rainer Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany

ISBN: (纸本)9781467322973;9781467322966

A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specification. This is accomplished by omitting redundant simulation steps occurring in the conventional architecture debug cycle. The potential speedup is demonstrated with a case study, achieving an acceleration of the debug cycle by 660x.

关键词： Integrated circuit design

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