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Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms 14

Neuronal connectivity assessment for epileptic seizure preve...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Georgis, Georgios Reisis, Dionysios Skordilakis, Panagiotis Tsakalis, Konstantinos Shafique, Ashfaque Bin Chatzikonstantis, George Lentaris, George Electronics Lab Faculty of Physics University of Athens Greece School of Electrical Computer and Energy Engineering Arizona State University United States Microlab School of Electrical and Computer Engineering University of Athens Greece

ISBN: (纸本)9781479937707

Research on the prevention of epileptic seizures has led to approaches for future treatment techniques, which rely on the demanding computation of generalized partial directed coherence (GPDC) on electroencephalogram (EEG) data. A fast computation of such metrics is a key factor both for the off-line optimization of algorithmic parameters and for its real-time implementation. Aiming at speeding up the GPDC computations on EEG data, the current paper presents massively parallel computational strategies for implementing the GPDC on many-core architectures. We apply the proposed strategies on commercial and experimental many-core platforms and we compare the results of the computation time of a set of EEG data on the Bulldozer and Ivy Bridge x86-64 serial processors. We test the GPUs of nVidia GTX 550 Ti and GTX 670, which at the best case achieve a significant speedup of 190x and 460x respectively. Moreover, we apply the proposed parallelization strategies on the Single-Chip Cloud computer (SCC), an experimental processor created by Intel Labs. © 2014 IEEE.

关键词： Real time control

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Design Space Exploration for Fair Resource-Allocated NoC architectures 14

Design Space Exploration for Fair Resource-Allocated NoC Arc...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Psathakis, Antonis Papaefstathiou, Vassilis Katevenis, Manolis Pnevmatikatos, Dionisios FORTH ICS Heraklion Iraklion Greece Univ Crete Dept Comp Sci Iraklion Greece Tech Univ Crete Dept Elect & Comp Engn Khania Greece

ISBN: (纸本)9781479937707

Networks-on-chip are integral parts of modern chips and designers explore the architectural design space to optimize both performance and energy-efficiency. Architectural choices for modern NoCs include: (i) partitioning using multiple subnetworks (P), (ii) concentration (C), and (iii) express physical links (X). Previous efforts do not adequately cover the design space while the range of assumptions vary significantly, rendering direct comparisons between different configurations impossible. This work expands the NoC design space and overcomes previous shortcomings by exploring the impact of architectural choices (P, C, X) separately and combinatorially on a 2D mesh. We generate all possible NoC configurations for large systems (64 and 256 nodes) and compare performance, energy, and area when the configurations utilize equal resources. First, we equalize the bisection wire count and analyze the impact of P, C, and X on NoC buffer space using analytical formulas. Then, we distribute an equal amount of buffer space in each NoC configuration by adjusting the respective router micro-architecture. Our results indicate that, with equal resources, none of the configurations exceeds the performance of the baseline 2D mesh. Moreover, we find that as node count increases to hundreds, the exclusive use of express physical links with an interval of 2 is the best approach in terms of energy and area. Furthermore, we observe that partitioning under equal buffer space and bisection bandwidth results in increased energy and area.

关键词： buffer space Space Exploration Equal increased energy Building design configurations partitions

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FPGA-SPICE: A simulation-based power estimation framework for FPGAs

FPGA-SPICE: A simulation-based power estimation framework fo...

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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli Integrated Systems Laboratory (LSI) Ecole Poly technique Federale de Lausanne (EPFL) Lausanne Vaud Switzerland

Mainstream Field Programmable Gate Array (FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models. The power consumption of the programmable resources of FPGAs is highly sensitive to their configurations. Due to their highly flexible nature, the configurations of FPGAs routing multiplexers or Look Up Tables (LUTs) are really different from a design to another but current analytical power models cannot accurately capture the associated power differences. In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language. Our power estimation engine automatically generates accurate SPICE netlists according to the FPGA configurations and enables precise power analysis of FPGA architectures. SPICE testbenches can be generated at different level of complexity, denoted as full-chip-level, grid-level and component-level testbenches. Full-chip-level testbenches dump the netlists associated with the complete FPGA fabric. To reduce simulation time, FPGA-SPICE can split the full-chip-level testbenches into grid-level testbenches, each of which consisting of a complete logic block netlist, or component-level testbenches, which consider individual circuit elements, i.e., multiplexers, LUTs, flip-flops, etc., separately. We show that the grid/component-level approach can achieve 14 × speed-up with a moderate 14% accuracy loss, compared to the full-chip level. We also use FPGA-SPICE to study the power characteristics of a commercial FPGA architecture at different technology nodes. Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs and flip-flops.

关键词： Field programmable gate arrays Routing Integrated circuit modeling Estimation SPICE Table lookup

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Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case 14

Automated Design Flow for Coarse-Grained Reconfigurable Plat...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sau, C. Raffo, L. Palumbo, F. Bezati, E. Casale-Brunet, S. Mattavelli, M. Univ Cagliari Dipartimento Ingn Elettr & Elettron I-09124 Cagliari Italy Univ Sassari Dipartimento Sci Polit & Comunicaz & Ingn Informa I-07100 Sassari Italy Ecole Polytech Fed Lausanne EPFL SCI STI MM CH-1015 Lausanne Switzerland

ISBN: (纸本)9781479937707

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform.

关键词： Design flow decoders configurability Platform MAPPING(MATHEMATICAL) Regional vital capacity REACTOR VOLUME CONTROL computer-Aided Design Moving Pictures Experts Group MPEG 4 Standard management of resources

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An ESL timing and power estimation and simulation framework for heterogeneous socs 14

An ESL timing and power estimation and simulation framework ...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Gruttner, Kim Hartmann, Philipp A. Fandrey, Tiemo Hylla, Kai Lorenz, Daniel Stattelmann, Stefan Sander, Bjorn Bringmann, Oliver Nebel, Wolfgang Rosenstiel, Wolfgang OFFIS Institute for Information Technology Eschwerweg 2 Oldenburg26121 Germany ABB Corporate Research Wallstadter Straße 59 Ladenburg68526 Germany Hitex Development Tools GmbH Greschbachstr. 12 Karlsruhe76229 Germany C.v.O. Universität Oldenburg Ammerländer Heerstr. 114-118 Oldenburg26111 Germany Universität Tübingen Sand 13 Tübingen72076 Germany

ISBN: (纸本)9781479937707

Consideration of an embedded system's timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard-and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable proto-types are generated from a functional C/C++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios. © 2014 IEEE.

关键词： Timing circuits

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Integrated Smart Grid simulations for Generic Automation architectures with RT-LAB and mosaik

Integrated Smart Grid Simulations for Generic Automation Arc...

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2014 IEEE international conference on Smart Grid Communications (SmartGridComm)

作者： Buescher, Martin Claassen, Arno Kube, Matthias Lehnhoff, Sebastian Piech, Klaus Rohjans, Sebastian Scherfke, Stefan Steinbrink, Cornelius Velasquez, Jorge Tempez, Francois Bouzid, Yahia OFFIS Inst Informat Technol R&D Div Energy Oldenburg Germany OPAL RT EUROPE Sceaux France

ISBN: (纸本)9781479949342

Although, a variety of established tools for analysis of power systems already exists, it is in the medium term very unlikely that one of these tools alone will provide all functionalities and models that are required to simulate future Smart Grids in all its facets. This is mainly due to the high number of Smart Grid use cases, actors, and technologies to be integrated that is not known from other industries so far. Accordingly, a mixture of various different and established tools will be required. These, again, have to be composed in use cases specific to complex and system-wide scenarios. Therefore, tools such as simulation platforms and -suites are required that are additionally capable of integrating software-and hardware models and components. Therefore, the proposed approach is an integrated concept allowing for analyzing large-scale scenarios taking into consideration both, stationary and dynamic simulations in real-time.

关键词： power systems smart power grids RT-LAB complex scenarios dynamic simulations generic automation architectures hardware models integrated smart grid simulations large-scale scenarios mosaik real-time system simulation platforms software models stationary simulations system-wide scenarios Computational modeling Couplings Hardware Load modeling Real-time systems Smart grids Software Smart grids real-time systems power systems Dynamic simulation Load modeling computer hardware Computational modeling Couplings hardware model computer software

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Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor 14

Dynamic-Vector Execution on a General Purpose EDGE Chip Mult...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Duric, Milovan Palomar, Oscar Smith, Aaron Stanic, Milan Unsal, Osman Cristal, Adrian Valero, Mateo Burger, Doug Veidenbaum, Alex Barcelona Supercomp Ctr Barcelona Spain Microsoft Res Redmond WA USA Univ Politecn Cataluna E-08028 Barcelona Spain Univ Illinois Urbana IL 61801 USA CSIC IIIA Barcelona Spain

ISBN: (纸本)9781479937707

This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP core to mimic the functionality of a vector processor. The morphing provides dynamic vector execution (DVX) on a general purpose CMP, by adding minimal hardware for vector control. DVX enhances the vector execution by dynamically configuring the allocation of compute and memory resources to match particular workload requirements. As an energy efficient substrate, we utilize modest dual issue cores based on an Explicit Data Graph Execution (EDGE) architecture. The results show that a DVX enabled 4-core EDGE CMP improves the energy-delay product over 14x, at the cost of only 1.1% of additional area. We compare DVX against a CMP that adds a dedicated DLP accelerator based on a conventional high performance vector design. The vector accelerator increases the area footprint over 74%, which greatly affects the cost of the modest processor. DVX avoids the additional costs and yet gains over 86% of the speedup obtained with the dedicated accelerator.

关键词： Basic metabolic panel cytidine monophosphate Chemical mechanical polishing telecommunication standards cellular radio Legal Executions Accelerators Multiprocessor Speeding 3G mobile communication edges TXNL4B gene digital light processor(DLP) computer chips DNA Microarrays

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simulation, modeling, and Programming for Autonomous Robots: 4th international conference, SIMPAR 2014, Bergamo, Italy, October 20-23, 2014. Proceedings 1

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丛书名： Lecture Notes in computer Science 8810 Lecture Notes in Artificial Intelligence

2014年

作者： Davide Brugali, Jan F. Broenink, Torsten Kroeger, Bruce A. MacDonald (eds.)

ISBN: (数字)9783319119007

ISBN: (纸本)9783319118994;9783319119007

This book constitutes the refereed proceedings of the 4th international conference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2014, held in Bergamo, Italy, in October 2014. The 49 revised full papers presented were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on simulation, modeling, programming, architectures, methods and tools, and systems and applications.

关键词： Autonomous robots Autonomous robots Robots simulation methods Programming

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Performance modeling of Virtualized Custom Logic Computations

Performance Modeling of Virtualized Custom Logic Computation...

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IEEE 25th international conference on Application-Specific systems, architectures and Processors (ASAP)

作者： Hall, Michael J. Chamberlain, Roger D. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)9781479936090

Virtualization of custom logic computations (i. e., by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context-switched to support virtualization using C-slow techniques (fine-grained context-switching) or by adding a secondary memory (coarse-grained context-switching). The performance of these computations depends on the circuit, technology, number of pipeline stages, number of streams, cost of a context switch, scheduling period, and arrival rate. In this paper, we analyze a virtualized hardware design and develop a set of analytic modeling equations for predicting the performance of these circuits. We then validate the model equations using a discrete-event simulation.

关键词： Virtualization context switching PERFORMANCE modeling rivers streams computer hardware design Customs hardware resource arrival rate Customization Formal logic pipeline circuit technique Electric circuits secondary memory

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Evaluating the memory system behavior of smartphone workloads 14

Evaluating the memory system behavior of smartphone workload...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Narancic, G. Judd, P. Wu, D. Atta, I. Elnacouzi, M. Zebchuk, J. Albericio, J. Enright Jerger, N. Moshovos, A. Kutulakos, K. Gadelrab, S. Department of Electrical and Computer Engineering University of Toronto Canada Department of Computer Science University of Toronto Canada Qualcomm Canada

ISBN: (纸本)9781479937707

Modern smartphones comprise several processing and input/output units that communicate mostly through main memory. As a result, memory represents a critical performance bottleneck for smartphones. This work1 introduces a set of emerging workloads for smartphones and characterizes the performance of several memory controller policies and address-mapping schemes for those workloads. The workloads include high-resolution video conferencing, computer vision algorithms such as upper-body detection and feature extraction, computational photography techniques such as high dynamic range imaging, and web browsing. This work also considers combinations of these workloads that represent possible use cases of future smartphones such as detecting and focusing on people or other objects in live video. While some of these workloads have been characterized before, this is the first work that studies address mapping and memory controller scheduling for these workloads. Experimental analysis demonstrates: (1) Most of the workloads are either memory throughput or latency bound straining a conventional smartphone main memory system. (2) The address mapping schemes that balance row locality with concurrency among different banks and ranks are best. (3) The FR-FCFS with write drain memory scheduler performs best, outperforming some more recently proposed schedulers targeted at multi-threaded workloads on general purpose processors. These results suggest that there is potential to improve memory performance and that existing schedulers developed for other platforms ought to be revisited and tuned to match the demands of such smartphone workloads. © 2014 IEEE.

关键词： Mapping

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