This book constitutes the refereed proceedings of the 4th internationalconference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2014, held in Bergamo, Italy, in October 2014. The 49 revised f...
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ISBN:
(数字)9783319119007
ISBN:
(纸本)9783319118994;9783319119007
This book constitutes the refereed proceedings of the 4th internationalconference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2014, held in Bergamo, Italy, in October 2014. The 49 revised full papers presented were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on simulation, modeling, programming, architectures, methods and tools, and systems and applications.
Virtualization of custom logic computations (i. e., by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context...
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ISBN:
(纸本)9781479936090
Virtualization of custom logic computations (i. e., by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context-switched to support virtualization using C-slow techniques (fine-grained context-switching) or by adding a secondary memory (coarse-grained context-switching). The performance of these computations depends on the circuit, technology, number of pipeline stages, number of streams, cost of a context switch, scheduling period, and arrival rate. In this paper, we analyze a virtualized hardware design and develop a set of analytic modeling equations for predicting the performance of these circuits. We then validate the model equations using a discrete-event simulation.
Modern smartphones comprise several processing and input/output units that communicate mostly through main memory. As a result, memory represents a critical performance bottleneck for smartphones. This work1 introduce...
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High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the Universit...
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ISBN:
(纸本)9781479927289
High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the University of Amsterdam. In previous work different levels of high-level simulation for instruction execution have been proposed, where the objective of every level is to keep the highest possible abstraction in order to achieve the least complexity and highest simulation speed with a compromise on the amount of accuracy. In this article we propose a new breakthrough in abstraction by simulating entire components in applications using analytical models. This simulation technique greatly reduces the complexity of the simulator and increases the simulation speed by orders of magnitude compared to the other levels of the high-level simulator, without affecting the simulation accuracy.
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as ...
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ISBN:
(纸本)9781479933785
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as performance evaluation, speedup and bottleneck analysis, and system verification by taking the advantages of exploring many-core platforms in different abstraction levels altogether. To demonstrate our methodology, a design framework is proposed, consisting of a scalable many-core processor architecture and a hardware-independent software layer. Based on the scalable architecture, the prototype platform is also presented in Electronic System Level (ESL) and Register Transfer Level (RTL). The platform integrates sixteen Processing Elements (PEs) and a 4-by-4 mesh-based network with external memory. Our hardware-independent software layer aims at realistic parallel applications in the baremetal environment, i.e., without an Operating System (OS). With the on-chip communication library and system utilities, software built on top of the fast ESL many-core platform can be executed seamlessly on the RTL one. The analysis shows that our ESL simulation model provides relatively accurate performance metrics as compared with the RTL implementation, with up to 773.8 times faster in terms of simulation speed. In addition, we showcase the study of speedup and bottleneck analysis, which justifies the effectiveness of our methodology for embedded applications in many-core architectures.
Tomlinson-Harashima precoding (THP) is an attractive non-linear interference cancellation method for multiple-input multiple-output (MIMO) system with decentralized receivers. Compared to linear methods, it is able to...
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Tomlinson-Harashima precoding (THP) is an attractive non-linear interference cancellation method for multiple-input multiple-output (MIMO) system with decentralized receivers. Compared to linear methods, it is able to achieve significant performance improvement while introduce negligible computational complexity increase. However, THP is sensitive to inevitable channel state information (CSI) errors at the transmitter in wireless communications. We statistically model the errors caused by channel estimation and feedback delay. By taking this modeling into account, we propose a flexible low-complexity compensation method for THP with imperfect CSI. In contrast to several robust designs optimized for one specific THP implementation, our approach can achieve average robustness for various THP implementations with negligible complexity overhead. Several canonical and emerging preprocessing algorithms, e.g, sorted QR decomposition (SQRD), vertical Bell Laboratories Space Time (V-BLAST) and lattice reduction (LR), are evaluated under a 802.11ac based MIMO OFDM simulation system. The experimental results show that the proposed compensation approach is able to lower the error floors caused by imperfect CSI significantly for various THP implementations.
This paper describes an efficient methodology based on the co-simulation between several software tools that has been developed to drive and increase the dynamic behavior of a Desktop Mechatronic Interface (DMI) for s...
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ISBN:
(纸本)9781479922802
This paper describes an efficient methodology based on the co-simulation between several software tools that has been developed to drive and increase the dynamic behavior of a Desktop Mechatronic Interface (DMI) for shape rendering. The co-simulation is performed by using a multi-body software, which is linked to MATLAB/Simulink. With the multi-body software the virtual simulation of the DMI is performed in order to sense the rotation angles of the virtual servo-actuators. By using this interaction it is possible to control the real servo-actuators presented in the DMI. In addition, through this methodology it is possible to perform experimental simulation in kinematics, dynamics and control of the DMI. A collision approach is presented taking into account both, friction and restitution coefficients which are required in the virtual simulation of the DMI. simulation results show that the co-simulation platform is established successfully.
DESERVE is a research project, started on September 2012, which will finish on August 2015. The project aims at designing and developing a Tool Platform for embedded Advanced Driver Assistance systems (ADAS) to exploi...
DESERVE is a research project, started on September 2012, which will finish on August 2015. The project aims at designing and developing a Tool Platform for embedded Advanced Driver Assistance systems (ADAS) to exploit the benefits of cross-domain software reuse, standardized interfaces, and easy and safety-compliant integration of heterogeneous modules to cope with expected increase of functions complexity and the impellent need of cost reduction.
Real-time hybrid simulation (RTHS) is an important tool in the design and testing of civil and mechanical structures when engineers and scientists wish to understand the performance of an isolated component within the...
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ISBN:
(纸本)9781450330527
Real-time hybrid simulation (RTHS) is an important tool in the design and testing of civil and mechanical structures when engineers and scientists wish to understand the performance of an isolated component within the context of a larger structure. Performing full-scale physical experimentation with a large structure can be prohibitively expensive. Instead, a hybrid testing framework connects part of a physical structure within a closed loop (through sensors and actuators) to a numerical simulation of the rest of the structure. If we wish to understand the dynamic response of the combined structure, this testing must be done in real-time, which significantly restricts both the size of the simulation and the rate at which it can be conducted. Adding parallelism to the numerical simulation can enable both larger and higher frequency real-time simulations, potentially increasing both the accuracy and the control stability of the test. We present a proof-of-concept exploration of the execution of real-time hybrid simulations (an exemplar of a more general class of cyber-mechanical systems) with parallel computations. We execute large numerical simulations within tight timing constraints and provide a reasonable assurance of timeliness and usability. We detail the operation of our system, its design features, and show how parallel execution could enable qualitatively better experimentation within the discipline of structural engineering.
In recent years several approaches for parallel SystemC simulation were proposed, which are mainly based on the synchronous parallel simulation *** propose a new simulation approach which uses the asynchronous paralle...
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In recent years several approaches for parallel SystemC simulation were proposed, which are mainly based on the synchronous parallel simulation *** propose a new simulation approach which uses the asynchronous parallel simulation principle. By using an appropriate modeling style where the communication is modeled by transaction events our kernel can exploit the inherent parallelism of simulation models. Experiments show that our approach can exploit the inherent parallelism in cases where the classical synchronous approach cannot. In this paper the underlying simulation algorithm and the modeling constructs are presented.
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