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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Trace-Driven Performance Estimation of Multi-core Platforms 57

Trace-Driven Performance Estimation of Multi-core Platforms

引用

57th IEEE international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Kim, Kyoungwon Gajski, Daniel D. Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)9781479941322

In hardware/software co-design for a multi-core platform, a crucial role is played by fast and accurate early performance estimation. One type of such estimation that is as fast as native simulation, cycle-approximate and applicable to both software and custom hardware is Transaction Level Model (TLM) Estimation that depends on TLM simulation. For every platform selection and mapping, however, the entire platform must be simulated. The simulation overhead is reduced by Trace-driven estimation but such estimation is not applicable to custom hardware and often requires Cycle Accurate Models (CAMs), which may not available for the whole platform. In this paper, we present Trace-Driven Performance Estimation (TDPE) of multi-core designs. TDPE is a trace-driven estimation but applicable to both software and hardware and requires no CAM. Since TDPE includes a mere single functional simulation, it is orders of magnitude faster than TLM Estimation. TLM Estimation is cycle-approximate by considering the data path of each Processing Element (PE), memory hierarchy, RTOS scheduling and overheads, bus arbitration and overhead. TDPE takes all of them into account so is as accurate as TLM Estimation.

关键词： Abstracts Computational modeling Delays Estimation Hardware Time-domain analysis Time-varying systems computer hardware Performance Evaluation Time domain analysis time-varying systems Computational modeling Platform bus arbitration delay computer aided manufacturing computer software

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Modelling and Stochastic simulation of Synthetic Biological Boolean Gates. 16

Modelling and Stochastic Simulation of Synthetic Biological ...

引用

16th IEEE international conference on High Performance Computing and Communications HPCC 2014\11th IEEE international conference on embedded Software and systems ICESS 2014\6th international Symposium on Cyberspace Safety and Security CSS 2014

作者： Sanassy, Daven Fellermann, Harold Krasnogor, Natalio Konur, Savas Mierla, Laurentiu M. Gheorghe, Marian Ladroue, Christophe Kalvala, Sara Newcastle Univ Sch Comp Sci Newcastle Upon Tyne Tyne & Wear England Univ Sheffield Sch Comp Sci Sheffield S Yorkshire England Univ Warwick Sch Comp Sci Coventry W Midlands England

ISBN: (纸本)9781479961238

Synthetic Biology aspires to design, compose and engineer biological systems that implement specified behaviour. When designing such systems, hypothesis testing via computational modelling and simulation is vital in order to reduce the need of costly wet lab experiments. As a case study, we discuss the use of computational modelling and stochastic simulation for engineered genetic circuits that implement Boolean AND and OR gates that have been reported in the literature. We present performance analysis results for nine different state-of-the-art stochastic simulation algorithms and analyse the dynamic behaviour of the proposed gates. Stochastic simulations verify the desired functioning of the proposed gate designs.

关键词： Computational modeling STOCHASTIC simulation gates simulating Stochastic Genetic Engineering modeling synthetic biology biological organs desired function LABORATORY SYSTEM Composing OR gates

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Research on Protection Methods of embedded Operating System Software Based on Hardware Compiler

引用

3rd international conference on computer-Aided Design, Manufacturing, modeling and simulation(CDMMS 2013)

作者： He, Gaoming Wuzhou Univ Dept Comp Sci Wuzhou 543002 Peoples R China

ISBN: (纸本)9783037859100

This paper describes a system;CODESSEAL can provide protection and evaluation to system software. CODESSEAL was designed to protect embedded systems with sufficient expertise and resources to capture attack equipment and manipulator, not only to protect software but also to protect hardware. By using the reconfigurable hardware allows CODES SEAL to provide confidentiality, integrity of security services and a platform-independent program flow without having to redesign the processor. System uses software and data protection technology and designs cycle simulation methods for data analysis. Experimental results show that the protected instructions and data with a high level of safety can be realized a low, which in most cases the performance loss can be reduced to below 10%, so the research of software protection methods of the embedded operating system of hardware compiler has important practical significance.

关键词： embedded Operating System Hardware Compiler FPGA

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Real Time simulation of a Turbine Bypass Controller 10

Real Time Simulation of a Turbine Bypass Controller

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IEEE/ASME 10th international conference on Mechatronic and embedded systems and Applications (MESA)

作者： Pugi, Luca Carcasci, Carlo Galardi, Emanuele Rindi, Andrea Lucchesi, Nicola Univ Florence DIEF Dept Ind Engn Florence Italy Velan AB SpA Lucca Italy

ISBN: (纸本)9781479922802

For a fast and safe start up and shut down of steam power plants, there is a growing interest in the optimization of turbine bypass controllers and actuators that are mainly used during transients. This work is focused on the development of a simple and fast code for Real Time (RT) simulation of a steam plant for the Hardware In the Loop (HIL) simulation of turbine bypass controllers and actuators. The aim is to build a Simulink library of simplified plant components such as valves, turbines, heaters and so on that could be easily assembled in order to simulate, with a very simplified approach, different plants and operating scenarios. The code is implemented for a fixed, discrete step solver and has been tested on a Texas Instrument DSP, as an example of low cost industrial hardware. In particular, two different uses of the developed code should be considered: the first one is the development of a virtual environment that should be used for HIL testing of controllers and actuators. The second one is the creation of RT models of complete plants or subsystems for the development of model based controllers.

关键词： Biological system modeling Boilers Computational modeling Turbines Valves Biological system modeling VALVE GATE turbines Boilers Computational modeling Controllers STEAM PLANT actuators boilers STEAM POWER PLANTS real-time simulation computer hardware Plant Components Fasting Shut down

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Parallel simulation of Superscalar Scheduling 43

Parallel Simulation of Superscalar Scheduling

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43rd Annual international conference on Parallel Processing (ICPP)

作者： Haugen, Blake Kurzak, Jakub YarKhan, Asim Luszczek, Piotr Dongarra, Jack Univ Tennessee Knoxville Innovat Comp Lab Knoxville TN 37996 USA Univ Manchester Oak Ridge Natl Lab Manchester M13 9PL Lancs England

ISBN: (纸本)9781479956180

computers have been moving toward a multicore paradigm for the last several years. As a result of the recent multicore paradigm shift, software developers must design applications that exploit the inherent parallelism of modern computing architectures. One of the areas of research to simplify this shift is the development of dynamic scheduling utilities that allow the developer to specify serial code that can be parallelized using a library or compiler technology. While these tools certainly increase the developer's productivity, they can obfuscate performance bottlenecks. For this reason, it is important to evaluate algorithm performance in order to ensure that the performance of a given algorithm is being realized using dynamic scheduling utilities. This paper presents the methodology and results of a new performance analysis tool that aims to accurately simulate the performance of various superscalar schedulers, including OmpSs, StarPU, and QUARK. The process begins with careful timing of each of the computational routines that make up the algorithm. The simulation tool then uses the timing of the computational kernels in conjunction with the dependency management provided by the superscalar scheduler in order to simulate the execution time of the algorithm. This tool demonstrates that simulation results of various algorithms can accurately predict the performance of a complex dynamic scheduling system.

关键词： multiprocessing systems parallel processing performance evaluation processor scheduling OmpSs QUARK StarPU algorithm performance evaluation complex dynamic scheduling system performance prediction computational kernels computational routines computing architectures dependency management dynamic scheduling utility development execution time simulation multicore paradigm parallel simulation tool parallelism serial code superscalar scheduling Computational modeling Kernel Libraries Linear algebra Multicore processing Parallel processing performance modeling simulation

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Vehicle-Hardware-In-The-Loop system for ADAS prototyping and validation

Vehicle-Hardware-In-The-Loop system for ADAS prototyping and...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Clément Galko Romain Rossi Xavier Savatier IRSEEM Systèmes Électroniques Embarqués France

This paper introduces an innovative system easing prototyping and validation of Advanced Driver Assistance systems (ADAS) for automotive applications. This system, based on a chassis-dynamometer and a multi-sensor simulation software, act as a virtual reality platform for intelligent vehicle. This system allows to test and validate complex ADAS systems under various simulated environmental conditions and scenario without the cost, complexity and hazard associated with test-drives. It can also be used early in the design process to test and validate the integration of multiple ADAS in a vehicle. This system is being used for the Virtual Testing applications in the DESERVE 1 project.

关键词： Vehicles Computational modeling Software Roads computers Cameras Real-time systems

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Functional modeling compiler for system-level design of automotive cyber-physical systems 33

Functional modeling compiler for system-level design of auto...

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2014 33rd IEEE/ACM international conference on computer-Aided Design, ICCAD 2014

作者： Canedo, Arquimedes Wan, Jiang Faruque, Mohammad Abdullah Al Siemens Corporation Corporate Technology United States University of California IrvineCA United States

ISBN: (纸本)9781479962785

A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preemptively target the concept design phase that determines 75% of a vehicle's cost. In our methodology, the marriage of systems engineering principles with high-level synthesis techniques results in a Functional modeling Compiler capable of generating high-fidelity simulation models for the design space exploration and validation of multiple cyber-physical (ECUs+Physics) vehicle architectures. Using real-world automotive use-cases, we demonstrate how functional models capturing cyber-physical aspects are synthesized into high-fidelity simulation models. © 2014 IEEE.

关键词： High level synthesis

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WCET-aware scheduling optimizations for multi-core real-time systems

WCET-aware scheduling optimizations for multi-core real-time...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Timon Kelter Hendrik Borghorst Peter Marwedel TU Dortmund University Dormund Germany

In real-time systems, the WCET (worst-case execution time) of tasks is of utmost importance. For multi-cores, the WCET has been shown to be hard to determine due to task interactions on shared memory and shared buses. This problem is usually addressed by spatial or temporal partitioning of the resources, but both lead to lower utilization if the partitioning is not done optimally. We examine two approaches for optimizing resource usage in a temporally partitioned multi-core system and show that these techniques can reduce the WCET by more than 30% on average, leading to better schedulability and higher system utilization.

关键词： Schedules Time division multiple access Computational modeling Benchmark testing Optimal scheduling Runtime

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An ID and address protection unit for NoC based communication architectures 14

An ID and address protection unit for NoC based communicatio...

引用

7th international conference on Security of Information and Networks, SIN 2014

作者： Saeed, Ahmed Ahmadinia, Ali Just, Mike Bobda, Christophe School of Engineering and Built Environment Glasgow Caledonian University Glasgow United Kingdom Department of Computer Science and Computer Engineering University of Arkansas FayettevilleAR United States

ISBN: (纸本)9781450330336

Security is becoming the primary concern in today's embedded systems. Network-on-Chip (NoC) based communication architectures have emerged as an alternative to shared bus mechanism in Multiprocessor System-on-Chip (MPSoC) devices, and the increasing number and functionality of processing cores has made such systems vulnerable to security attacks. In this paper an id and address verification (IAV) security module is presented, which is embedded in each router at the communication level. IAV verifies the identity and address range to be accessed by incoming and outgoing data packets in a NoC-based many-core shared memory architecture. Our IAV architecture is implemented on a FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyse the performance overhead for different network configurations. The proposed IAV module has reduced area and power consumption overhead when compared with similar existing solutions. Copyright 2014 ACM 978-1-4503-3033-6/14/09Ě$15.00.

关键词： Network-on-chip

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Combining application adaptivity and system-wide Resource Management on multi-core platforms

Combining application adaptivity and system-wide Resource Ma...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Giuseppe Massari Edoardo Paone Patrick Bellasi Gianluca Palermo Vittorio Zaccaria William Fornaciari Cristina Silvano DEIB Politecnico di Milano Milano Italy

To better exploit the capabilities offered by multi-core high-end embedded systems, new parallel programming paradigms, such as OpenCL, combined with effective resource management should be adopted. However, dealing with mixed workloads and time varying scenarios is still an open problem. This paper addresses such challenges by exploiting the synergy between Design Space Exploration and Run-Time Resource Management to achieve effective and flexible system-wide application adaptivity. The proposed approach and related toolset have been validated on a multi-core NUMA platform, showing significant improvements in terms of QoS and resource utilization compared to conventional application-level optimization strategies.

关键词： Optimization Computational modeling Resource management Space exploration Measurement computer architecture Proposals

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