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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath

Synthesis of Instruction Extensions on HyperCell, a reconfig...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Kavitha T. Madhu Saptarsi Das C. Madhava Krishna S. Nalesh S.K. Nandy Ranjani Narayan Indian Institute of Science Bangalore India Indian Institute of Science Bangalore Karnataka IN Morphing Machines Pvt. Ltd Bangalore India

In this paper we present HyperCell as a reconfigurable datapath for Instruction Extensions (IEs). HyperCell comprises an array of compute units laid over a switch network. We present an IE synthesis methodology that enables post-silicon realization of IE datapaths on HyperCell. The synthesis methodology optimally exploits hardware resources in HyperCell to enable software pipelined execution of IEs. Exploitation of temporal reuse of data in HyperCell results in significant reduction of input/output bandwidth requirements of HyperCell.

关键词： Switches Hardware Registers Schedules Arrays Fabrics Computational modeling

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Architectural low-power design using transaction-based system modeling and simulation

Architectural low-power design using transaction-based syste...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Fabian Mischkalla Wolfgang Mueller University of Paderborn C-LAB Paderborn Germany

Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.

关键词： Time-varying systems Time-domain analysis Computational modeling Mathematical model Semantics Switches Standards

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Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs

Co-exploration of NLA kernels and specification of Compute E...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Mahesh Mahadurkar Farhad Merchant Arka Maity Kapil Vatwani Ishan Munje Nandhini Gopalan S K Nandy Ranjani Narayan CADLab Indian Institute of Science Bangalore India Morphing Machines Pvt. Ltd. BITS Pilani

Coarse Grained Reconfigurable architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi-core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

关键词： Matrix decomposition Kernel Algorithm design and analysis Computational modeling Memory management Registers

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Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations

Highly-parallel special-purpose multicore architecture for S...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： N. Ventroux J. Peeters T. Sassolas James C. Hoe Computer Architecture Laboratory (CALCM) Carnegie Mellon University Pittsburgh PA USA CEA LIST Embedded Computing Laboratory Gif-sur-Yvette CEDEX France

The complexity of SystemC virtual prototyping is continuously increasing. Accelerating RTL/TLM SystemC simulations is essential to control future SoC development cost and time-to-market. In this paper, we present RAVES, a highly-parallel special-purpose multicore architecture that achieves simulation performance more efficiently by parallel execution of light-weight user-level threads on many small cores. We present a design study based on the virtual prototype of RAVES processors running a co-designed custom SystemC kernel. Our evaluation suggests that a 64-core RAVES processor can deliver up to 4.47× more simulation performance than a high-end x86 processor.

关键词： Kernel Instruction sets Benchmark testing Multicore processing Hardware

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Ranking software components using a modified PageRank algorithm including safety aspects

Ranking software components using a modified PageRank algori...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dominik Reinhardt Software-Architecture and Platform Software BMW Group Munich Germany

Automotive software is increasing rapidly in its size, amount or complexity and the demand for calculation power rises. According ISO26262, additional non-functional requirements for safety-relevant applications must be considered. Therefore, analyzing software networks is necessary to identify problems within an early development state. For future multicore systems, complex software structures probably impede a safe segregation of software components between cores. In this paper, we want to use social network measurement methods to analyze automotive software architectures. Here, the interconnection of single software components and their influence within the network is focused. We use a modification of Google's PageRank algorithm, where websites partly inherit the rank of their interlinked neighboring websites, and transfer these techniques to automotive needs. For our evaluation, we use data structures of an exemplary electronic control unit of BMW.

关键词： Software Safety Automotive engineering Software algorithms Multicore processing Computational modeling Vectors

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modeling of embedded system using SysML and its parallel verification using DiVinE tool

Modeling of embedded system using SysML and its parallel ver...

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14th international conference on Computational Science and Its Applications, ICCSA 2014

作者： Basit Ur Rahim, Muhammad Abdul Arif, Fahim Ahmad, Jamil Military College of Signals National University of Science and Technology Islamabad Pakistan Research Center for Modeling and Simulation National University of Science and Technology Islamabad Pakistan

ISBN: (纸本)9783319091556

SysML is a modeling language that can be used for the modeling of embedded systems. It is rich enough to model critical and complex embedded systems. The available modeling tools have made the modeling of such large and complex systems much easier. They provide sufficient support for the specification of functional requirements in the elicitation phase as well as in the design phase by graphical modeling. These systems must be properly validated and verified before their manufacturing and deployment in order to increase their reliability and reduce their maintenance cost. In this paper, we have proposed a methodology for the modeling and verification of embedded systems in parallel and distributed environments. We demonstrate the suitability of the framework by applying it on the case study of embedded security system. The parallel model checking tool DiVinE has been used because the available sequential verification tools either fail or show poor performance. DiVinE supports Linear Temporal Logic (LTL) for defining nonfunctional requirements and DVE language for specifying models. First,the case study is modeled using SysML's state machine diagrams and then semantics are described to translate these state machine diagrams to DVE based model. The translated model is verified against specified LTL properties using DiVinE. © 2014 Springer international Publishing.

关键词： embedded systems

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A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications

A comprehensive ASIC/FPGA prototyping environment for explor...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Florian Giesemann Guillermo Payá-Vayá Holger Blume Matthias Limmer Werner Ritter Institute of Microelectronic Systems Leibniz Universität Hannover Hannover Germany Vision Enhancement Daimler AG Ulm Germany

The development of complex algorithms for advanced driver assistance systems is a challenging task, due to the high innovation rate and processing demands of applications in this field. The development is usually supported by a software development framework that provides an infrastructure (e.g., access to sensor data) that simulates and evaluates the algorithms. One problem, especially with computationally intensive algorithms, is the slow simulation speed. This paper presents a prototyping environment that connects a software development framework with a FPGA-based hardware platform. This allows implementing computationally intensive tasks in hardware. The proposed rapid prototyping system not only reduces the simulation time, thereby allowing the software designer to evaluate algorithmic parameters with quicker feedback, but also allows verifying and evaluating hardware modules for rapid prototyping. A case study is presented in which a traffic sign detection algorithm is implemented on a soft-core processor. By using the hardware implementation the simulation was accelerated by a factor of 65, compared to the pure software implementation.

关键词： Hardware Software Software algorithms Field programmable gate arrays Algorithm design and analysis Computational modeling Pins

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Definition of an embedded driver model for driving behavior prediction within the DESERVE platform

Definition of an embedded driver model for driving behavior ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Jens Klimke Philipp Themann Christoph Klas Lutz Eckstein Institut für Kraftfahrzeuge (ika) Advanced Driver Assistance Systems Aachen Germany

The use of driver models within advanced driver assistance systems (ADAS) allows anticipating the driving behavior of the vehicle and all traffic participants in the close vicinity. This valuable information could considerably improve the performance as well as the acceptance of ADAS. Consequently complex driver models need to be integrated in embedded systems. This work, first of all, aims to summarize important driver models described in literature. Based upon this a suitable approach to implement a driver model on an embedded system is derived. The model used, focuses on the longitudinal driving and lane change behavior of drivers. The system architecture is derived and optimized for real-time execution. The driver model is analyzed in detailed simulations. Test drives in a small scale naturalistic driving study are used to validate the driver model. This paper defines a standard driver model to be implemented as part of the DESERVE platform within the Artemis project “DESERVE”. As embedded automotive hardware the dSpace MicroAutoBox II is used. The paper summarizes approaches and examples to use the generated prediction data in ADAS like ACC.

关键词： Vehicles Acceleration Computational modeling Mathematical model Roads Adaptation models Predictive models

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Speculative synchronization for coherence-free embedded NUMA architectures

Speculative synchronization for coherence-free embedded NUMA...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dimitra Papagiannopoulou Tali Moreshet Andrea Marongiu Luca Benini Maurice Herlihy R. Iris Bahar Department of Computer Science School of Engineering Providence RI USA Department of Engineering Swarthmore College Swarthmore PA USA Department of Engineering ETH Zurich Switzerland

High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access (NUMA) costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These “coherence-free” systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both useability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds new challenges in the design of hardware speculative support. In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. To the best of our knowledge, this is the first design for speculative synchronization for this type of architecture. Through a set of benchmark experiments using our simulation platform, we show that our design can achieve significant performance improvements over traditional lock-based schemes.

关键词： computer architecture Synchronization Hardware Program processors embedded systems Computational modeling Protocols

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Robustness analysis of multiprocessor schedules

Robustness analysis of multiprocessor schedules

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Shreya Adyanthaya Zhihui Zhang Marc Geilen Jeroen Voeten Twan Basten Ramon Schiffelers Eindhoven University of Technology Eindhoven The Netherlands TNO-ESI Eindhoven The Netherlands ASML Veldhoven The Netherlands

Tasks executing on general purpose multiprocessor platforms exhibit variations in their execution times. As such, there is a need to explicitly consider robustness, i.e., tolerance to these fluctuations. This work aims to quantify the robustness of schedules of directed acyclic graphs (DAGs) on multiprocessors by defining probabilistic robustness metrics and to present a new approach to perform robustness analysis to obtain these metrics. Stochastic execution times of tasks are used to compute completion time distributions which are then used to compute the metrics. To overcome the difficulties involved with the max operation on distributions, a new curve fitting approach is presented using which we can derive a distribution from a combination of analytical and limited simulation based results. The approach has been validated on schedules of time-critical applications in ASML wafer scanners.

关键词： Robustness Schedules Computational modeling Histograms Measurement Analytical models Approximation methods

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