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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms

Performance evaluation of the Intel Xeon Phi manycore archit...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Oliver Jakob Arndt Daniel Becker Florian Giesemann Guillermo Payá-Vayá Christopher Bartels Holger Blume Leibniz Universität Hannover Institute of Microelectronic Systems Hanover Germany Corporate Technology Siemens AG Munich Germany

Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore and manycore processors can execute a diversity of software applications (e.g, driver assistance systems) written in portable high-level programming languages resulting in less porting effort at lower costs for power-consumption tolerant fields. For instance, the Intel Xeon Phi manycore processor featuring 61 cores offers not only a high theoretical peak performance but also a supportive tool chain for the software development in high-level programming languages. In contrast to traditional general-purpose multicore processors, this manycore architecture, however, exhibits different processor characteristics, inter-core communication topologies, and instruction sets. In this paper, we introduce the parallel implementation of a histogram of oriented gradients algorithm for pedestrian detection. Using a parallel semi-global matching algorithm as well, serving as an additional driver assistance algorithm, we present an in-depth performance analysis case study on the Intel Xeon Phi and also note distinct characteristics of this target platform. To allow a fair comparison, we not only rate an Intel Xeon 16-core general-purpose processor, but also present a platform comparison to customized hardware architectures.

关键词： Program processors Histograms Feature extraction Vectors Multicore processing Computational modeling

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Modelica modeling Language as a Tool on Control Engineering Education: simulation of a Two-Tank System

Modelica Modeling Language as a Tool on Control Engineering ...

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international conference on Teaching, Assessment and Learning (TALE)

作者： Figueiredo, Joao Carvalho, Vitor Machado, Jose Soares, Filomena Polytech Inst Cavado & Ave Sch Technol Barcelos Portugal Univ Minho Algoritmi Res Ctr Res Ctr CT2M Guimaraes Portugal

ISBN: (纸本)9781479976720

Cross education to diverse areas of Engineering requires innovation in the used resources. Thus, the process of simulation proves to be fundamental to a first approach of complex physical systems prior to implementation Moreover, the fact that sometimes there is a reduced time to combine a strong practical component to lectures makes use of tools such as virtual laboratories and remote laboratories essential to education. This paper demonstrates how simulation of a closed system, via the embedded programming language Modelica in the Dymola Software, allows the production of reliable and robust controllers to illustrate the simulation methodology oriented to education.

关键词： Modelica Dymola Control Education simulation

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RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs

RuRot: Run-time rotatable-expandable partitions for efficien...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Syed M. A. H. Jafri Guilermo Serrano Junaid Iqbal Masoud Daneshtalab Ahmed Hemani Kolin Paul Juha Plosila Hannu Tenhunen Turku Centre for Computer Science Royal Institute of Technology Sweden University of Turku Finland Universidad Politcnica de Valencia Spain Indian Institute of Technology Delhi

Today, Coarse Grained Reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Compile-time mapping decisions are neither optimal nor desirable to efficiently support the diverse and unpredictable application requirements. As a solution to this problem, recently proposed architectures offer run-time remapping. The run-time remappers displace or expand (parallelize/serialize) an application to optimize different parameters (such as platform utilization). However, the existing remappers support application displacement or expansion in either horizontal or vertical direction. Moreover, most of the works only address dynamic remapping in packet-switched networks and therefore are not applicable to the CGRAs that exploit circuitswitching for low-power and high predictability. To enhance the optimality of the run-time remappers, this paper presents a design framework called Run-time Rotatable-expandable Partitions (RuRot). RuRot provides architectural support to dynamically remap or expand (i.e. parallelize) the hosted applications in CGRAs with circuit-switched interconnects. Compared to state of the art, the proposed design supports application rotation (in clockwise and anticlockwise directions) and displacement (in horizontal and vertical directions), at run-time. simulation results using a few applications reveal that the additional flexibility enhances the device utilization, significantly (on average 50 % for the tested applications). Synthesis results confirm that the proposed remapper has negligible silicon (0.2 % of the platform) and timing (2 cycles per application) overheads.

关键词： computer architecture Calculators Integrated circuit interconnections Computational modeling Parallel processing Indexes Hardware

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An automotive specific MILP model targeting power-aware function partitioning

An automotive specific MILP model targeting power-aware func...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Gregor Walla Andreas Herkersdorf André S. Enger Andreas Barthels Hans-Ulrich Michel Technische Universitaet Muenchen Institute for Integrated Systems Munich Germany Technische Universitaet Muenchen Institute for Informatics Munich Germany BMW Group Research and Technology Munich Germany

With customer demand for more comfort and safety features, the amount of software and electronics in a car is steadily growing. In order to cope with the corresponding increased power consumption of the E/E (electric/electronic) architecture, various power saving techniques were developed to turn off functions, electronic control units (ECUs), or even whole bus systems when they are temporarily not needed. However, the potential of these techniques is highly dependent on the mapping of the vehicle functions to the distributed network of ECUs. This paper presents a mixed-integer linear programming (MILP) approach that supports the designer in an early phase of the automotive E/E development process to find an optimal function partitioning with respect to energy-efficiency. While various MILP-based task to processor mapping concepts have been investigated before, the contribution of this paper brings forward an automotive domain specific MILP model with a cost function that is based on the power consumption for computation and communication of the overall system. Furthermore, the schedulability of the partitions is here taken into account. The approach was integrated into an existing E/E design space exploration framework and evaluated for feasibility and scalability. The results reflect the potential gain of a power-aware function partitioning.

关键词： Transceivers computer architecture Computational modeling Automotive engineering Power demand Vehicles Schedules

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4th international conference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2014

4th International Conference on Simulation, Modeling, and Pr...

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4th international conference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2014

The proceedings contain 50 papers. The special focus in this conference is on Statistical Language and Speech Processing. The topics include: Making time make sense in robotic simulation;a dynamic simulator for underwater vehicle-manipulators;control and scheduling co-design for a simulated quadcopter robot: a model-driven approach;simulating human-robot interactions for dialogue strategy learning;a simulation based architecture for the development of an autonomous all terrain vehicle;applying simulation and a domain-specific language for an adaptive action library;analysis of knee-ankle orthosis modelling: an inverse dynamics approach using adaptive coupled oscillator;optimizing robotic team performance with probabilistic model checking;fault avoidance in development of robot motion-control software by modeling the computation;robotic engineer’s specifications for a well-fitted model-driven control architecture for robots;a survey on domain-specific languages in robotics;towards rule-based dynamic safety monitoring for mobile robots;a proposed software framework aimed at energy-efficient autonomous driving of electric vehicles;structured design and development of domain-specific languages in robotics;robot unit testing;declarative specification of robot perception architectures;a modeling framework for software architecture specification and validation;reverse engineering of middleware for verification of robot control architectures;an extensible software architecture for composing motion and task planners;merging partially consistent maps;lower limb stiffness estimation during running: the effect of using kinematic constraints in muscle force optimization algorithms;on the benefits of component-defined real-time visualization of robotics software;a primate-inspired autonomous navigation algorithm using the cognitive mechanism of mental rotation and the cognitive interaction toolkit – improving reproducibility of robotic systems experiments.

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Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Dynamic-vector execution on a general purpose EDGE chip mult...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Milovan Duric Oscar Palomar Aaron Smith Milan Stanic Osman Unsal Adrian Cristal Mateo Valero Doug Burger Alex Veidenbaum Barcelona Supercomputing Center Universitat Politècnica de Catalunya Microsoft Research CSIC-IIIA University of Illinois at Urbana-Champaign

This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP core to mimic the functionality of a vector processor. The morphing provides dynamic vector execution (DVX) on a general purpose CMP, by adding minimal hardware for vector control. DVX enhances the vector execution by dynamically configuring the allocation of compute and memory resources to match particular workload requirements. As an energy efficient substrate, we utilize modest dual issue cores based on an Explicit Data Graph Execution (EDGE) architecture. The results show that a DVX enabled 4-core EDGE CMP improves the energy-delay product over 14x, at the cost of only 1.1% of additional area. We compare DVX against a CMP that adds a dedicated DLP accelerator based on a conventional high performance vector design. The vector accelerator increases the area footprint over 74%, which greatly affects the cost of the modest processor. DVX avoids the additional costs and yet gains over 86% of the speedup obtained with the dedicated accelerator.

关键词： Vectors Registers Hardware computer architecture Instruction sets Message systems Computational modeling

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Resource conscious prefetching for irregular applications in multicores

Resource conscious prefetching for irregular applications in...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Muneeb Khan Erik Hagersten Department of Information Technology Uppsala University Sweden

Many real-world applications exhibit irregular memory access patterns that cannot be handled by stream prefetchers in commodity processors. While it is possible to target irregular accesses by prefetching them in software, doing so requires a low-overhead method that ensures last-level cache and off-chip bandwidth friendly prefetching of useful data. Further, to make such approaches practical, they should ideally not require access to source code. In this work we present a low-overhead software-only method for efficient prefetching of irregular memory access patterns. The method is targeted at commodity multicores and designed to conserve shared last level cache space and off-chip bandwidth. Our approach uses low-overhead runtime sampling and statistical cache modeling to identify irregular loads that frequently miss in the cache. A cost-benefit analysis then identifies the irregular loads that can benefit from prefetching in software. This approach allows us to improve average single thread performance across 10 workloads by 10%, without dramatically increasing the off-chip bandwidth. We evaluate our method on two commodity multicores. Across 210 multi-process runs that utilize a multicore by running several different workloads in parallel, the proposed irregular software prefetching mechanism achieves up to 22% better throughput than hardware prefetching. All workload mixes benefit from our scheme, improving throughput by 9% on average.

关键词： Prefetching Load modeling Runtime Bandwidth Multicore processing Computational modeling

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Multi-FPGA prototyping board issue: the FPGA I/O bottleneck

Multi-FPGA prototyping board issue: the FPGA I/O bottleneck

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Qingshan Tang Habib Mehrez Matthieu Tuna Laboratoire Informatique Paris-6 Université Pierre et Marie CURIE Paris France Flexras Technologies Paris France

Multi-FPGA boards are widely used for rapid system prototyping. As the ratio between the logic capacity and the number of I/Os for each FPGA generation is increasing, FPGA I/Os are becoming a scarce resource. In order to resolve pin limitation problem, cut nets are sent between FPGAs in a pipelined way using the Time-Division-Multiplexing technique. The maximum number of cut nets passing through one FPGA I/O is called the TDM ratio. There are three inter-FPGA communication architectures: Logic Multiplexing, ISERDES/OSERDES and Multi-Gigabit Transceiver (MGT). Only Logic Multiplexing and ISERDES/OSERDES are today used for Time-Division-Multiplexing in the multi-FPGA based prototyping. In this paper, the achieved performance of Logic Multiplexing and ISERDES/OSERDES is compared in different TDM ratios and a hybrid multiplexing architecture using both ISERDES/OSERDES and MGT is proposed. Experiments are done in a multi-FPGA board with the testbench LFSR to validate the achieved performance. The results show that even though consuming more FPGA I/Os for data transmission, ISERDES/OSERDES can achieve higher performance than Logic Multiplexing. The proposed architecture can achieve higher performance than ISERDES/OSERDES when the TDM ratio exceeds 54. The maximum gain in performance is about 20%.

关键词： Field programmable gate arrays Synchronization Clocks Time division multiplexing Delays computer architecture

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modeling the temperature bias of power consumption for nanometer-scale CPUs in application processors

Modeling the temperature bias of power consumption for nanom...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Karel DeVogeleer Gerard Memmi Pierre Jouvelot Fabien Coelho TELECOM ParisTech Paris ÃŽle-de-France FR TELECOM ParisTech UMR Paris France MINES ParisTech France

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20°C to 85°C temperature range. Our data suggest that, for application processors operating between 20°C and 50°C, a quadratic model is still accurate and a linear approximation is acceptable.

关键词： Temperature measurement Leakage currents Program processors Heating Voltage control Computational modeling Temperature distribution

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Design space exploration for fair resource-allocated NoC architectures

Design space exploration for fair resource-allocated NoC arc...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Antonis Psathakis Vassilis Papaefstathiou Manolis Katevenis Dionisios Pnevmatikatos Dept. of Computer Science University of Crete Heraklion Greece FORTH-ICS Heraklion Crete Greece Dept. of Electronic and Computer Engineering Technical University of Crete Chania Greece

Networks-on-chip are integral parts of modern chips and designers explore the architectural design space to optimize both performance and energy-efficiency. Architectural choices for modern NoCs include: (i) partitioning using multiple sub-networks (P), (ii) concentration (C), and (iii) express physical links (X). Previous efforts do not adequately cover the design space while the range of assumptions vary significantly, rendering direct comparisons between different configurations impossible. This work expands the NoC design space and overcomes previous shortcomings by exploring the impact of architectural choices (P, C, X) separately and combinatorially on a 2D mesh. We generate all possible NoC configurations for large systems (64 and 256 nodes) and compare performance, energy, and area when the configurations utilize equal resources. First, we equalize the bisection wire count and analyze the impact of P, C, and X on NoC buffer space using analytical formulas. Then, we distribute an equal amount of buffer space in each NoC configuration by adjusting the respective router micro-architecture. Our results indicate that, with equal resources, none of the configurations exceeds the performance of the baseline 2D mesh. Moreover, we find that as node count increases to hundreds, the exclusive use of express physical links with an interval of 2 is the best approach in terms of energy and area. Furthermore, we observe that partitioning under equal buffer space and bisection bandwidth results in increased energy and area.

关键词： Wires Computational modeling computer architecture Ports (computers) computers Artificial neural networks Delays

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