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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Massively parallel signal processing challenges within a driver assistant prototype framework first case study results with a novel MIMO-radar

Massively parallel signal processing challenges within a dri...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Frank Meinl Martin Kunert Holger Blume Robert Bosch GmbH Leonberg Germany Institute of Microelectronic Systems Leibniz Universität Hannover

Real-time constraints, mounting space and power limitations of radar sensors and its corresponding signal processing needs are always in conflict with the available computational requirements. This paper presents a prototype design for a heterogeneous MIMO-Radar system that automatically scales with the amount of prevailing data throughput. An important measure is to partition the different processing units of the radar system according to the characteristics of the consecutive signal processing steps. These characteristics range from low-level, massive parallel number crunching to very complex, more stream-oriented and often branching high-level tasks with sophisticated reasoning and decision taking. The handling and real-time processing of extremely high data-rates in the order of tens of Gigabit per second is a new aspect that can only be solved outside the familiar and typically used PC-based development platforms. A new hardware framework is introduced that enables rapid prototyping of a computational very intensive real time system on a FPGA based processing unit. With the help of cost model based design space exploration (DSE) techniques it becomes possible to estimate the hardware effort of such a system in its very early development stage. The necessary cost models for a DSE of the challenging signal processing blocks of a MIMO radar will be derived in future work to further improve the design process.

关键词： Radar Chirp Radar antennas Field programmable gate arrays Computational modeling Real-time systems Sensors

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A system-level simulation framework for evaluating task migration in MPSoCs

A system-level simulation framework for evaluating task migr...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Wei Quan Andy D. Pimentel School of Computer Science National University of Defense Technology Hunan China Informatics Institute University of Amsterdam The Netherlands

Task migration is the transfer of the execution of a process (task) from one processing element to another. It originates from the massive deployment of distributed systems in the parallel computing field to enable dynamic load distribution, fault resilience and to enhance data access locality. With the development of MultiProcessor System-on-Chip (MPSoC) architectures, the topic of task migration has recently regained research interest in the embedded systems domain. In this paper, we present a high-level simulation framework to study task migration for MPSoC systems. With this framework, different migration methodologies on different underlying hardware systems can be easily and rapidly modeled, simulated and evaluated during the early stages of design. By using this high-level simulation framework, a designer can study the migration impact on the overall performance of the system by exploring different task migration mechanisms (determining what and how to migrate) or using different migration policies (determining when to migrate which tasks whereto) in a specific task migration mechanism. Using a number of experiments, we demonstrate the capabilities of our simulation framework.

关键词： Program processors computer architecture Hardware Context Computational modeling Communication channels Load modeling

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A hybrid control architecture for autonomous mobile robot navigation in unknown dynamic environment

A hybrid control architecture for autonomous mobile robot na...

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IEEE international conference on Automation Science and Engineering

作者： Danial Nakhaeinia Pierre Payeur Tang Sai Hong Babak Karasfi School of Electrical Engineering and Computer Science University of Ottawa University Putra Malaysia

ISBN: (纸本)9781467381840

This paper introduces a new hybrid control architecture for solving the navigation problem of mobile robot in an unknown dynamic environment based on an actual-virtual target switching strategy. This hybrid architecture is a combination of deliberative and reactive architectures which consists of three layers: modeling, planning and reaction. The deliberative architecture produces collision-free with shortest-distance path, while using the reactive architecture generates safe and time minimal navigation path. The proposed approach differs from previous ones in its integration architecture, the control techniques implemented in each module, and interfaces between the deliberative and reactive components. Validity and feasibility of the proposed approach are verified through simulation and real robot experiments.

关键词： Robot sensing systems Robot kinematics Collision avoidance Navigation computer architecture Planning

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Fine-grained link locking within power and latency transaction level modelling in wormhole switching non-preemptive networks on chip 14

Fine-grained link locking within power and latency transacti...

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5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core architectures and 3rd Workshop on Design Tools and architectures for Multicore embedded Computing Platforms, PARMA-DITAM 2014

作者： Harbin, James Indrusiak, Leandro Soares Department of Computer Science Real Time Systems Group University of York United Kingdom

ISBN: (纸本)9781450326070

An increasingly time-consuming part of the design flow of on-chip multiprocessors is simulation of the network on chip (NoC) architecture. Cycle-accurate simulation of state-of-the art network-on-chip interconnects can be prohibitively slow for realistic application examples. In this paper, we identify a time-predictable non-preemptive network-on-chip architecture and propose a TLM model with fine-grained locking of links. The model is tested via simulation of two benchmark application scenarios. Results demonstrate that the proposed algorithm can model the latency upon the majority of flows very closely to the cycle-accurate model, while providing more than 97% accurate power consumption modelling even on the worst case links. This is achieved while simulating nearly three orders of magnitude faster compared to a cycle-accurate model of the same interconnect. Copyright © 2014 ACM.

关键词： Network-on-chip

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4th international conference on computer-Aided Design, Manufacturing, modeling and simulation, CDMMS 2014

4th International Conference on Computer-Aided Design, Manuf...

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4th international conference on computer-Aided Design, Manufacturing, modeling and simulation, CDMMS2014

ISBN: (纸本)9783038351528

The proceedings contain 227 papers. The special focus in this conference is on Advanced Developments of CAx, Modelling and simulation Technologies in Manufacturing, Information System Design and Development, Networks Applications, Modern Methods of Intelligent Automation, Data Mining and Processing and Methodologies, Devices and embedded Tools, Technologies of Measurement, Diagnosis and Testing. The topics include: Solid modeling and optimization design of crank rocking flying shear;research on modeling design in composite molding;research on integrated simulation of space robot mission;emergency supplies demand forecasting model;research on service capability based on data mining;design of new double-wing product drop test machine;mechanical industrial design in product development;mobile network application engine design based on android system;research on audio retrieval based on content;design of laboratory management system based on web;research of data exchange model among information systems;study on the architecture of mobile campus digital library system;image edge detection based on solitary wave algorithm;research on computer network security and prevention strategy;analysis and dispose of deviation of mine belt conveyor;research on reservoir heterogeneity of complex region;study on process and defect of arc welding;frequency measurement method based on signal delay detection;analysis on voltage and reactive power in civil lighting;research of ITO transparent conductive;application of carbon capture and sequestration in clean energy cycle technology;analysis of meteorological data sharing system;study on earthquake of fault based on GIS and study on sedimentary characteristics and models of river group sequence.

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The DESERVE project: Towards future ADAS functions

The DESERVE project: Towards future ADAS functions

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Matti Kutila Pasi Pyykönen Paul van Koningsbruggen Nereo Pallaro Joshué Pérez-Rastelli VTT Technical Research Centre of Finland Tampere Finland Technolution B.V. Gouda the Netherlands Centro Ricerche FIAT Turin Italy INRIA Le Chesnay Cedex France

This article introduces the objectives and structure of the European research project DESERVE that is co-funded by the ARTEMIS-JU and national funding bodies. The project started in September 2012 with a duration of 3 years. The project aims to establish a new embedded SW and HW design by using a more efficient development process (including the enabling general platform concept and tool chain) in order to overcome challenges in reducing component costs and development time of future ADAS functions for modern vehicles. Both the process and the platform concept will be demonstrated with innovative ADAS functions in 3 passenger cars, 1 truck and 1 motorcycle. embedded hardware and software units have been developed for improving electronic horizon band of vehicles by detecting objects in front. Moreover, driver/motorcycle rider awareness is analysed by monitoring his/her actions online. The systems need to be robust and reliable in different environment conditions (night time, rain, etc.). The DESERVE platform distinguishes three layers of intelligence: perception, application and intervention&warning control. The demonstrators will be based on software development tools from Elektrobit (ADTF) and Intempora (RTmaps). These tools are used to create 10 innovative ADAS applications as part of an integral ADAS development platform, following a new design and development process. Since the project is highly application oriented, the requirements have been adapted mainly from the ISO 26262 standard and the AUTOSAR framework which ensures compatibility with the existing automotive software environment.

关键词： Software Safety Motorcycles Computational modeling Monitoring Automotive engineering

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Integrating Graph Transformations and Modal Sequence Diagrams for Specifying Structurally Dynamic Reactive systems 8

Integrating Graph Transformations and Modal Sequence Diagram...

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8th international conference on System Analysis and modeling (SAM)

作者： Winetzhammer, Sabine Greenyer, Joel Tichy, Matthias Univ Bayreuth Chair Appl Comp Sci 1 Software Engn Univ Str 30 D-95440 Bayreuth Germany Leibniz Univ Hannover Software Engn Grp D-30167 Hannover Germany Univ Gothenburg Software Engn Div S-41296 Gothenburg Sweden

ISBN: (纸本)9783319117430;9783319117423

Software-intensive systems, for example service robot systems in industry, often consist of multiple reactive components that interact with each other and the environment. Often, the behavior depends on structural properties and relationships among the system and environment components, and reactions of the components in turn may change this structure. Modal Sequence Diagrams (MSDs) are an intuitive and precise formalism for specifying the interaction behavior among reactive components. However, they are not sufficient for specifying structural dynamics. Graph transformation rules (GTRs) provide a powerful approach for specifying structural dynamics. We describe an approach for integrating GTRs with MSDs such that requirements and assumptions on structural changes of system resp. environment objects can be specified. We prototypically implemented this approach by integrating MOD-GRAPH with SCENARIOTOOLS. This allows us not only to specify MSDs and GTRs in Eclipse, but also to simulate the specified behavior via play-out.

关键词： scenario-based specification reactive systems embedded systems automotive simulation validation testing

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Evaluating the memory system behavior of smartphone workloads

Evaluating the memory system behavior of smartphone workload...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： G. Narancic P. Judd D. Wu I. Atta M. Elnacouzi J. Zebchuk J. Albericio N. Enright Jerger A. Moshovos K. Kutulakos S. Gadelrab Department of Electrical and Computer Engineering University of Toronto Department of Computer Science University of Toronto Qualcomm

Modern smartphones comprise several processing and input/output units that communicate mostly through main memory. As a result, memory represents a critical performance bottleneck for smartphones. This work 1 introduces a set of emerging workloads for smartphones and characterizes the performance of several memory controller policies and address-mapping schemes for those workloads. The workloads include high-resolution video conferencing, computer vision algorithms such as upper-body detection and feature extraction, computational photography techniques such as high dynamic range imaging, and web browsing. This work also considers combinations of these workloads that represent possible use cases of future smartphones such as detecting and focusing on people or other objects in live video. While some of these workloads have been characterized before, this is the first work that studies address mapping and memory controller scheduling for these workloads. Experimental analysis demonstrates: (1) Most of the workloads are either memory throughput or latency bound straining a conventional smartphone main memory system. (2) The address mapping schemes that balance row locality with concurrency among different banks and ranks are best. (3) The FR-FCFS with write drain memory scheduler performs best, outperforming some more recently proposed schedulers targeted at multi-threaded workloads on general purpose processors. These results suggest that there is potential to improve memory performance and that existing schedulers developed for other platforms ought to be revisited and tuned to match the demands of such smartphone workloads.

关键词： Computational modeling Cameras Decoding Modems Face Streaming media computer architecture

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20th international conference on Parallel Processing, Euro-Par 2014

20th International Conference on Parallel Processing, Euro-P...

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20th international conference on Parallel Processing, Euro-Par 2014

ISBN: (纸本)9783319098722

The proceedings contain 68 papers. The special focus in this conference is on Support tools environments, Performance prediction and evaluation, Scheduling and load balancing, High performance architectures and compilers, Parallel and distributed data management, Grid, Cluster and cloud computing, Green high performance computing, Distributed systems and algorithms, Parallel and distributed programming, Parallel numerical algorithms, Multicore and manycore programming, Theory and algorithms for parallel computation and High performance networks and communication. The topics include: MPI trace compression using event flow graphs;customized scalable tracing with in-situ data analysis;performance measurement and analysis of transactional memory and speculative execution on IBM blue Gene/Q;an open-source management framework for cloud applications;modeling and simulation of a dynamic task-based runtime system for heterogeneous multi-core architectures;modeling the impact of reduced memory bandwidth on HPC applications;finding the important basic blocks in multithreaded programs;optimization and trade-off analysis for time, energy and resource usage;performance prediction and evaluation of parallel applications in KVM, Xen, and VMware;per-task DRAM energy metering in multicore systems;characterizing the performance-energy tradeoff of small ARM cores in HPC computation;finding efficient queue setup using high-resolution simulations;a progressively pessimistic scheduler for software transactional memory;a queueing theory approach to pareto optimal bags-of-tasks scheduling on clouds;scheduling/placement approach for task-graphs on heterogeneous architecture;energy-aware multi-organization scheduling problem;energy efficient scheduling of mapreduce jobs and switchable scheduling for runtime adaptation of optimization.

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Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Automated design flow for coarse-grained reconfigurable plat...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： C. Sau L. Raffo F. Palumbo E. Bezati S. Casale-Brunet M. Mattavelli Dipartimento di Ingegneria Elettrica ed Elettronica Universitá degli studi di Cagliari Italy Dipartimento di Scienze Politiche e della Comunicazione e Ingegneria dell' Informazione Universitá degli studi di Sassari Italy EPFL SCI STI MM Ecole Polytechnique Fédérale de Lausanne Switzerland

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform.

关键词： Decoding Transform coding Hardware Computational modeling Standards Clocks computers

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