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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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A run-time modulo scheduling by using a binary translation mechanism

A run-time modulo scheduling by using a binary translation m...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ricardo Ferreira Waldir Denver Monica Pereira Jorge Quadros Luigi Carro Stephan Wong Departamento Informatica UFV Vicosa Brazil Departamento de Informatica e Matematica Aplicada UFRN Natal RN Brazil Instituto de Informatica UFRGS Porto Alegre Brazil Computer Engineering Lab TU Delft Delft Netherlands

It is well known that innermost loop optimizations have a big effect on the total execution time. Although CGRAs is widely used for this type of optimizations, their usage at run-time has been limited due to the overheads introduced by application analysis, code transformation, and reconfiguration. These steps are normally performed during compile time. In this work, we present the first dynamic translation technique for the modulo scheduling approach that can convert binary code on-the-fly to run on a CGRA. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated (from one memory access per cycle to two memory accesses per cycle). Moreover, a comparison to the state-of-the-art static compiler-based approaches for inner loop accelerators has been done by using CGRA and VLIW as target architectures. Additionally, to measure area and performance, the proposed CGRA was prototyped on a FPGA. The area comparisons show that crossbar CGRA (with 16 processing elements) is 1.9x larger than the VLIW 4-issue and 1.3x smaller than a VLIW 8-issue softcore processor, respectively. In addition, it reaches an overall speedup factor of 2.17x and 2.0x in comparison to the 4 and 8-issue, respectively. Our results also demonstrate that the run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for an n-issue VLIW processor.

关键词： Registers computer architecture Clocks VLIW Computational modeling Vectors Software

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Source code annotated memory leak detection for soft real time embedded systems with resource constraints 12

Source code annotated memory leak detection for soft real ti...

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IEEE 12th international conference on Dependable, Autonomic and Secure Computing (DASC)

作者： Joy, Mabel Mary Mueller, Wolfgang Rammig, Franz Josef Univ Paderborn C Lab Paderborn Germany Univ Paderborn Heinz Nixdorf Inst Paderborn Germany

ISBN: (纸本)9781479950799

With ever increasing complexity of software and increased competition in the market, it is very important to minimize the production to market delivery time. Early phase detection of serious errors in the design and program can be done with automated approaches which save time. Memory leaks are the most important memory related problems which are severe threats to software applications. We propose a novel hybrid automated source code annotated memory leak detection approach for soft real time embedded system software with no garbage collection. We utilize our source code annotation tool to detect the potential memory leak candidates, which are further analyzed in our hybrid leak detection approach. The control flow graph of the source code generated with our annotation tool provides information of all execution paths, where the basic blocks are annotated with specific marks. Our hybrid method combines static and dynamic approaches. Static phase of the hybrid approach detect the potential leak candidates from the control flow graph. Dynamic phase filters false positives from the static phase results and provide results on the actual leaks. In early design stages where a real execution environment and complete executable software are unavailable, a simulation environment and a virtual platform are necessary. Virtual platforms provide flexibility to change the target architecture to be tested. Our proposed dynamic phase of the approach runs on the virtual memory model platform we implemented in SystemC at an abstract level using Transaction Level modeling. The software under test is run on top of this model. This makes our approach faster and provides early results. Our approach can be easily deployed across a variety of architectures as it is compiler independent and does not implement any architecture specific features. Moreover the automated approach provides an efficient methodology to determine potential leaks in early phases of software development.

关键词： Memory leak Soft real time system Virtual memory model Source code annotation Hybrid leak detection

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23rd international conference on Software Engineering and Data Engineering, SEDE 2014

23rd International Conference on Software Engineering and Da...

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23rd international conference on Software Engineering and Data Engineering, SEDE 2014

ISBN: (纸本)9781880843963

The proceedings contain 28 papers. The topics discussed include: cost-based evaluation and measurement for SaaS in the cloud;needs analysis phase of a cooperative information system using viewpoints;framework for open and distributed software architecture evaluation;reverse engineering - a survey of tools involved in reverse engineering;a single-factor dynamic authentication for computer systems with touch screens;DDoS attack and interception resistance IP fast hopping based protocol;developing complexity metrics to predict the usability of graphical user interfaces;performance verification and validation of discrete event simulation tools for large scale computer architectures;restaurant online ordering system with personalized advertising through data mining;xml based model language design and software development tool;a performance-guaranteed approximate range query algorithm for the ND-tree;and modeling of inter-cloud architecture using UML 2.0: multi-agent abstraction based approach.

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The Role of modeling and simulation in Coordination of Health Care 4

The Role of Modeling and Simulation in Coordination of Healt...

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4th international conference on simulation and modeling Methodologies, Technologies and Applications, SIMULTECH 2014

作者： Zeigler, Bernard P. Arizona Center for Integrative Modeling and Simulation U. Arizona TucsonAZ United States RTSync Corp PhoenixAZ United States

ISBN: (纸本)9789897580383

US healthcare, the most expensive in the world, has been diagnosed as an assemblage of uncoordinated component systems embedded in a market economy that promotes independent pricing with few points of global control over delivered quality of care and cost. Stimulated by the Affordable Care Act and other initiatives, efforts are underway to increase the level of information technology (IT) to improve patient record keeping and portability as well as to price services based on performance rather than amount provided. Yet such an IT infrastructure by itself will not provide significantly greater component coordination since it does not provide transparency into the threads of transactions that represent patient treatments, their outcomes, and total costs. In the traditional formulation of the coordination problem, the goal of the system-of-systems conflicts with those of its components. In contrast, our concern here is the coordination of activities among disconnected provider systems to deliver the appropriate services to an individual client. In this paper, we discuss the Pathways Coordination model, a generic construct that enforces threaded distributed tracking of individual patients experiencing certain pathways of intervention, thereby supporting coordination of care and fee-for-performance based on end-to-end outcomes. DEVSbased modeling and simulation methodology is discussed as the means to design, simulate, and implement such client-based coordination in systems engineering. © 2014 SciTePress. All rights reserved.

关键词： Costs

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Integrated Formal Methods - 11th international conference, IFM 2014, Proceedings

Integrated Formal Methods - 11th International Conference, I...

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11th international conference on Integrated Formal Methods, IFM 2014

ISBN: (纸本)9783319101804

The proceedings contain 23 papers. The topics discussed include: shape and content: a database-theoretic perspective on the analysis of data structures;how to break the bank: semantics of capability policies;model-checking circus state-rich specifications;an analysis pathway for the quantitative evaluation of public transport systems;modeling UML template classes with focalize;integrating event-B modelling and discrete-event simulation to analyse resilience of data stores in the cloud;applying an integrated modelling process to run-time management of many-core systems;verifying behavioral UML systems via CEGAR;verifying modal workflow specifications using constraint solving;managing LTL properties in event-B refinement;a probabilistic framework for security scenarios with dependent actions;towards a formal semantics-based technique for interprocedural slicing;integrating software and hardware verification;and verifying linearizability on TSO architectures.

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Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs

Fast Dynamic Binary Rewriting for flexible thread migration ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Giorgis Georgakoudis Dimitrios S. Nikolopoulos Hans Vandierendonck Spyros Lalis Queen's University of Belfast University of Thessaly Queen's University of Belfast University of Thessaly

Heterogeneous MPSoCs where different types of cores share a baseline ISA but implement different operational accelerators combine programmability with flexible customization. They hold promise for high performance under power and area limitations. However, transparent binary execution and dynamic scheduling is hard on those platforms. The stateof-the-art approach for transparent accelerated execution is fault-and-migrate (FAM): when a thread executes an accelerating instruction unavailable on the host core, it is forcibly migrated to an accelerating core which implements the instruction natively. Unfortunately, this approach prohibits dynamic scheduling through flexible thread migration, which is essential to any asymmetric platform for efficient utilization of heterogeneous resources. We present two distinct binary-level techniques - Dynamic Binary Rewriting (DBR) and Dynamic Binary Translation (DBT) - which enable selective acceleration, while preserving transparent thread execution and migration, to any core in the system, at any point in time. DBR rewrites binary code to exploit any accelerating instructions available in the host core. DBT implements a-fault-and-rewrite scheme, which sets up trampolines to emulation routines for these accelerating instructions which are not available on the host core. Both methods customize binary code on demand, enabling flexible migration. We evaluate the overhead of DBR and DBT against FAM on a real hardware shared-ISA MPSoC prototype. Experiments with single-thread programs show flexible migration is possible with manageable overhead. We measure the performance of our binary-level techniques by artificially triggering periodic thread migration between a Base and an accelerating (ACC) core. Periodic migration, without aiming for optimized scheduling, results in an average slowdown of about 40% under DBR or about 10% under DBT, compared to FAM driven scheduling. We also show results for a speedup proportional dynamic scheduler

关键词： Distributed Bragg reflectors Acceleration Emulation Benchmark testing Software Dynamic scheduling computer architecture

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An archimate based analysis of microgrid control system architectures

An archimate based analysis of microgrid control system arch...

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international conference on embedded systems (ICES)

作者： M. Välja N. Honeth M. Buschle R. Lagerström K. K. Sasi S. Nithin Industrial Information and Control Systems KTH - the Royal Institute of Technology Stockholm Sweden Electrical & Electronics Engineering Amrita University Coimbatore India

The architectures containing embedded systems such as microgrid controllers are becoming more complex. While there are several known methodologies for embedded system modeling and design, they mostly cover development related performance issues. There exists a gap in the management of architectures implementing embedded systems for power systems applications. This paper proposes to use enterprise architecture analysis, based on earlier work, to fill that gap. Availability, interoperability and cost analysis are in focus. Enterprise architecture models are important in order to abstract the technical detail for planning and design in order to provide a basis for discussion of technical scalability and cost management amongst stakeholders and technical experts. A microgrid control architecture based example is given to illustrate the analysis possibilities.

关键词： computer architecture Microgrids embedded systems Unified modeling language Analytical models Control systems Business

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SimLuator: A multi-core CPU simulator with dynamic language Lua 4

SimLuator: A multi-core CPU simulator with dynamic language ...

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4th international conference on simulation and modeling Methodologies, Technologies and Applications, SIMULTECH 2014

作者： Ye, John Li, Songyuan Chen, Tianzhou Wu, Minghui Liu, Li College of Computer Science Zhejiang University Hangzhou China College of Information Engineering North China University of Technology Beijing China City College Zhejiang University Hangzhou China School of Information Zhejiang Sci-Tech University Hangzhou China

ISBN: (纸本)9789897580383

For CPUs and SoCs (System on Chip) of recent years, their numbers of cores keep growing, and their designs become more and more complicated. It is desirable to model and simulate them easier, but existing simulators are usually big, complicated, hard to understand and even harder to modify. Plenty of efforts of CPU architecture researchers are spent on understanding the simulators rather than implementing any innovative improvements to the architectures. This paper tries to implement a simulator with Lua. Unlike C-family languages that most simulators are built with, Lua is a dynamic language, which is easier to program. As for our simulator, we tried to model a Speculative Multi-Threading (SpMT) processor with less than 800 lines of code. And with Just In Time (JIT) compiling technology, the simulator performs in a reasonable speed. We would like to share our experience with the CPU architecture research community, and encourage to use dynamic languages for rapid development of simulators, especially for initial exploration of innovative architectures. © 2014 SciTePress. All rights reserved.

关键词： Simulators

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modeling and simulation of electric power substation employing an IEC 61850 network 14

Modeling and simulation of electric power substation employi...

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9th Annual Cyber and Information Security Research conference, CISRC 2014

作者： Nivethan, Jeyasingam Papa, Mauricio Hawrylak, Peter Tandy School of Computer Science 800 South Tucker Drive Tulsa OK United States Department of Electrical and Computer Engineering 800 South Tucker Drive Tulsa OK United States

ISBN: (纸本)9781450328128

The timely delivery of messages is an important requirement in networks used to control physical processes such as those found in the Critical Infrastructure. These systems are also known as Process Control systems (PCS) or Supervisory Control and Data Acquisition (SCADA) systems. In the electric power sector, the IEC 61850 family of standards defines the network protocol for communication between devices inside an electric substation and the interface the substation presents to the Internet (outside world) in the Smart Grid. IEC 61850 uses IEEE 802.3 Ethernet for the physical and data link layers as opposed to the previous generation substations, which used dedicated point-to-point connections between devices. IEC 61850 (and other industrial protocols) operate in an environment where messages must arrive in time to be processed and action taken by control equipment. Discrete event simulation is a widely used technique to evaluate performance of such systems. Cyber attacks on process control systems often aim at overloading a communications link. This type of cyber attack may negatively affect such physical processes by introducing delays in messages that carry control actions. Ultimately, this type of attack may also result in a complete DoS situation. Therefore, from a security perspective, it is important to understand the impact that link load changes may have on the control system. This paper presents an OPNET Modeler simulation library to help analyze network traffic in electric power substations that employ the IEC 61850 standard for communication and control. This library is then used to examine sample substation network architectures to determine if they meet the message delivery performance requirements. Copyright is held by the owner/author(s).

关键词： Electric substations

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Proceedings - 2008 international conference on embedded computer systems: architectures, modeling, and simulation, IC-SAMOS 2008

Proceedings - 2008 International Conference on Embedded Comp...

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2008 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2008

ISBN: (纸本)9781424419852

The proceedings contain 28 papers. The topics discussed include: Picoserver- building a compact energy efficient multiprocessor;challenges in embedded system simulation;towards unified mechanisms for inter-processor communication;a general model of concurrency and its implementation as many-core dynamic RISC processors;a parameterized dataflow language extension for embedded streaming systems;an architecture for the simultaneous execution of hard real-time threads;an adaptive bloom filter cache partitioning scheme for multicore architectures;realizing reconfigurable mesh algorithms on softcore arrays;a light-weight network-on-chip architecture for dynamically reconfigurable systems;systematic design space exploration for customisable multi-processor architectures;and clustering method for the identification of convex disconnected multiple input multiple output instructions.

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