This demo shows how the development of Ambient Assisted Living systems can be enhanced with the assistance of agent technology. Concretely, this demo introduces advances in the PHAT framework to create what we call Vi...
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The increase in the amount of functionalities provided by safety-critical systems in the last years has lead to a complexity growth in these systems. Several techniques have been developed in order to tackle this issu...
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The increase in the amount of functionalities provided by safety-critical systems in the last years has lead to a complexity growth in these systems. Several techniques have been developed in order to tackle this issue, including simplification strategies and the definition of time-deterministic models of computation (MoCs) and architectures, such as the Logical Execution Time MoC (LET) and the Time-Triggered Architecture (TTA) respectively. Although TTA based systems relying on the LET MoC have already been successfully applied to safety-critical systems, SystemC, the nowadays de-facto standard in HW/SW system development, does not provide a LET-based simulation engine for the modeling and assessment of these systems. With the aim to fill this gap, this paper presents the PI-TTM, a novel SystemC extension for the modeling and simulation of LET based safety-critical embeddedsystems.
For productivity and correctness of embedded software system, I will focus on the verification of modeling by using M&S (modeling & simulation) in the modeling part. M&S (modeling & simulation) will be...
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For productivity and correctness of embedded software system, I will focus on the verification of modeling by using M&S (modeling & simulation) in the modeling part. M&S (modeling & simulation) will be used to verify the modeling. If models are simulated for verification after modeling when we develop the embedded software, we may have the correctness of models. Also, it is probably going to improve embedded software's reusability and reliability because we will be reusing correctness models. In this paper, we will extend a dynamic diagram of UML2.0 and xUML including Real-Time concepts to adapt to the embedded environment for embedded software modeling. Furthermore, it is probably going to improve reliability of embedded software system with using modeling and simulation concepts.
architectures are common means for organizing coordination between components in order to build complex systems and to make them manageable. Despite the progress of the state of the art over the past decades, there ar...
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architectures are common means for organizing coordination between components in order to build complex systems and to make them manageable. Despite the progress of the state of the art over the past decades, there are still a lot of foundational issues that remain unsolved. In this talk we present a general framework for modelingarchitectures and their properties.
MISR architectures are proposed to remove the unknown (X) values in the output sequences. The MISR signature is represented as a system of linear equations in terms of unknown's (X). The method of symbolic simulat...
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ISBN:
(纸本)9781479936984
MISR architectures are proposed to remove the unknown (X) values in the output sequences. The MISR signature is represented as a system of linear equations in terms of unknown's (X). The method of symbolic simulation is used to represent each bit of the MISR signature. The combination of linear equations of the MISR signature bits is determined with Gauss-Jordan Elimination algorithm to remove unknown values in the output responses. These X-cancelled combinations are then computed in a separate storage register to provide X-free combinations values. Experimental result describes that maximum error coverage and test time can be obtained with the help of theses MISR architectures.
The simulation of fine-grained latency tolerance based on the dynamic state of the system in high-level simulation of many-core systems is a challenging simulation problem. We have introduced a high-level simulation t...
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The simulation of fine-grained latency tolerance based on the dynamic state of the system in high-level simulation of many-core systems is a challenging simulation problem. We have introduced a high-level simulation technique for microthreaded many-core systems based on the assumption that the throughput of the program can always be one cycle per instruction as these systems have fine-grained latency tolerance. However, this assumption is not always true if there are insufficient threads in the pipeline and hence long latency operations are not tolerated. In this paper we introduce Signatures to classify low-level instructions in high-level categories and estimate the performance of basic blocks during the simulation based on the concurrent threads in the pipeline. The simulation of fine-grained latency tolerance improves accuracy in the high-level simulation of many-core systems.
A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preem...
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A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preemptively target the concept design phase that determines 75% of a vehicle's cost. In our methodology, the marriage of systems engineering principles with high-level synthesis techniques results in a Functional modeling Compiler capable of generating high-fidelity simulation models for the design space exploration and validation of multiple cyber-physical (ECUs+Physics) vehicle architectures. Using real-world automotive use-cases, we demonstrate how functional models capturing cyber-physical aspects are synthesized into high-fidelity simulation models.
Virtualization of custom logic computations (i.e, by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context-s...
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Virtualization of custom logic computations (i.e, by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context-switched to support virtualization using C-slow techniques (fine-grained context-switching) or by adding a secondary memory (coarse-grained context-switching). The performance of these computations depends on the circuit, technology, number of pipeline stages, number of streams, cost of a context switch, scheduling period, and arrival rate. In this paper, we analyze a virtualized hardware design and develop a set of analytic modeling equations for predicting the performance of these circuits. We then validate the model equations using a discrete-event simulation.
Use of polymer material in manufacturing of microstructures has been a trend in recent MEMS technology. One such trend is employed in this paper where in four different micro structures are designed and simulated usin...
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Use of polymer material in manufacturing of microstructures has been a trend in recent MEMS technology. One such trend is employed in this paper where in four different micro structures are designed and simulated using SU8 polymer material. All the architectures are simulated using COMSOL Multi physics to compute modal frequency. The simulation results are verified analytically using a standard mathematical equations. The simulated architectures are then modelled using neural network to compute the dimensions of a given architecture for a desired modal frequency. Also the simulation results, the analytical results and the ANN results are compared for the various architectures.
A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Functional Reconfiguration theoretical concepts are ...
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A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Functional Reconfiguration theoretical concepts are proposed to describe this kind of architectures, based on concepts from functional programming theory. A high-level design methodology is adapted and modified to allow easy design, testing and simulation. The architectural concepts are tested on an application domain and several tools are created to partially automate application mapping flow and system integration. Moreover, due to its inherent 3D structure of the proposed architecture, physical implementation into 3D silicon is attempted.
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