A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Functional Reconfiguration theoretical concepts are ...
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A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Functional Reconfiguration theoretical concepts are proposed to describe this kind of architectures, based on concepts from functional programming theory. A high-level design methodology is adapted and modified to allow easy design, testing and simulation. The architectural concepts are tested on an application domain and several tools are created to partially automate application mapping flow and system integration. Moreover, due to its inherent 3D structure of the proposed architecture, physical implementation into 3D silicon is attempted.
In this paper, an effective online method used for finite-horizon, nonlinear, stochastic tracking problems, is presented. The method incorporates the finite-horizon State Dependent Riccati Equation (SDRE) with Kaiman ...
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In this paper, an effective online method used for finite-horizon, nonlinear, stochastic tracking problems, is presented. The method incorporates the finite-horizon State Dependent Riccati Equation (SDRE) with Kaiman filter to account for the stochastic environment thereby extending the application spectrum to nonlinear systems and overcoming the hurdle with linear tracking systems limited to small variations around the operating point. The method is illustrated by both computersimulation and experimental verification via hardware in the loop simulation (HILS).
High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the Universit...
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High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the University of Amsterdam. In previous work different levels of high-level simulation for instruction execution have been proposed, where the objective of every level is to keep the highest possible abstraction in order to achieve the least complexity and highest simulation speed with a compromise on the amount of accuracy. In this article we propose a new breakthrough in abstraction by simulating entire components in applications using analytical models. This simulation technique greatly reduces the complexity of the simulator and increases the simulation speed by orders of magnitude compared to the other levels of the high-level simulator, without affecting the simulation accuracy.
The design of the network in distributed embeddedsystems often necessitates the analysis of its HW/SW tradeoffs along with network tradeoffs. To do so, a framework is presented to perform joint exploration of both HW...
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ISBN:
(纸本)9781450324717
The design of the network in distributed embeddedsystems often necessitates the analysis of its HW/SW tradeoffs along with network tradeoffs. To do so, a framework is presented to perform joint exploration of both HW/SW and network (NW) design spaces. In the proposed approach, UML+Profiles are used to model the whole system and SystemC code generation mechanism is exploited to validate it. SystemC-based HW/SW and NW simulators are integrated and used to simulate the overall system model. Design tradeoffs of HW/SW and NW are characterized to define the overall joint design space. In order to validate the proposed framework, an example of automotive application is used to explore several performance metrics and show how the framework is able to find the optimal set of design parameters.
We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influence...
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We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.
Specifying and modeling Quality of Service (QoS) properties represents a key challenge for cyber physical system development. Quality of Service (QoS) is a general term that specifies system quality and performance, a...
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ISBN:
(纸本)9781479932801
Specifying and modeling Quality of Service (QoS) properties represents a key challenge for cyber physical system development. Quality of Service (QoS) is a general term that specifies system quality and performance, as opposed to system functionality of cyber physical systems. QoS specification is concerned with capturing application level QoS requirements and management policies of cyber physical systems. Architecture Analysis and Design Language (AADL) is a textual and graphic language used to design and analyze the software and hardware architectures of embedded and realtime systems for performance-critical characteristics (e.g., end-to-end latency, schedulability, and reliability), AADL supports the representation of end-to-end flows through the concept of a flow specification This paper proposes an approach to specify and model QoS based on AADL. We present our current effort to apply and extend AADL to specify and model QoS of cyber physical systems, finally, we illustrate QoS specifying and modeling via an example of specifying and modeling Vehicular Ad-hoc NETwork (VANET).
Service Oriented Architecture (SOA) has been widely applied in a range of systems such as embeddedsystems, Enterprise Information systems and Cyber Physical systems. These systems nowadays show System of systems (SoS...
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Service Oriented Architecture (SOA) has been widely applied in a range of systems such as embeddedsystems, Enterprise Information systems and Cyber Physical systems. These systems nowadays show System of systems (SoS) characteristics including large-scale, consisting of software and hardware components, and cooperative processes among independent systems. It is very important to validate functional requirements and evaluate non-functional requirements of systems precisely in earlier design phase by executable architecting methodology. This paper aims to provide an executable modeling approach to SOA by bringing together Model Driven Service Engineering (MDSE) with Service oriented architecture modeling Language (SoaML) and modeling & simulation methodology based on Discrete Event System Specification (DEVS). First, the business architecture and system architecture are built with SoaML, then the Extended DEVS modeling Language (E-DEVSML) is used as a model transformation intermediary to make SOA models executable in an automated code generation process, finally, the early validation and evaluation of this SOA are done through a generated DEVS simulation. To demonstrate the applicability of this approach we introduce an aircraft docking process in an airport scenario as the case study.
To satisfy the ever increasing performance requirement of applications, Multiprocessor System-on-Chip (MPSoC) plays an irreplaceable role in embedded system these days. It is significant to effectively optimize commun...
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ISBN:
(纸本)9781479939541
To satisfy the ever increasing performance requirement of applications, Multiprocessor System-on-Chip (MPSoC) plays an irreplaceable role in embedded system these days. It is significant to effectively optimize communication for achieving maximum parallelism on MPSoC, especially on Network-on-Chip (NoC) based architectures. The problem of how to make an arbitration of communication congestion is remained unsolved. In this paper, we propose a reasonable Unified Priority-Based Scheduling (UPS) algorithm for task and communication co-scheduling with communication contention, which is based on a novel Task Communication Graph (TCG) model of an application. The proposed method is more accurate and effective to describe the overall process of applications. The experimental results show that the performance is improved by 31.1% on average of scheduling generated by our algorithm. It verifies that the proposed method in this paper can improve the performance of contention-aware task and communication scheduling on NoC-based MPSoC architecture.
With the rapid development of embedded technology, embeddedsimulation technology also followed it. In this paper, with single chip microcomputer of 8051 as an example, it introduces an implementation process of 8051 ...
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With the rapid development of embedded technology, embeddedsimulation technology also followed it. In this paper, with single chip microcomputer of 8051 as an example, it introduces an implementation process of 8051 simulation kernel by using discrete event model and object-oriented modeling approach, then a comprehensive test of the 8051 system kernel was tested to verify the reasonableness of the core model.
Due to the ever increasing constraints on power consumption in embeddedsystems, this paper addresses the need for an efficient power modeling and estimation methodology based tool at system-level. On the one hand, to...
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ISBN:
(纸本)9781450324717
Due to the ever increasing constraints on power consumption in embeddedsystems, this paper addresses the need for an efficient power modeling and estimation methodology based tool at system-level. On the one hand, today's embedded industries focus more on manufacturing RISC processor-based platforms as they are cost and power effective. On the other hand, modern embedded applications are becoming more and more sophisticated and resource demanding: multimedia (H.264 encoder and decoder), software defined radio, GPS, mobile applications, etc. The main objective of this paper focuses on the scarcity of a fast power modeling and an accurate power estimation tool at the system-level for complex embeddedsystems. In this paper, we propose a standalone simulation tool for power estimation at system-level. As a first step, we develop the power models at the functional level. This is done by characterizing the power behavior of RISC processor based platforms across a wide spectrum of application benchmark to understand their power profile. Then, we propose power models to cost-effectively estimate its power at run-time of complex embedded applications. The proposed power models rely on a few parameters which are based on functional blocks of the processor architecture. As a second step, we propose a power estimation simulator which is based on cycle-accurate full system simulation framework. The combination of the above two steps provides a standalone power estimation tool at the system-level. The effectiveness of our proposed methodology is validated through an ARM9, an ARM Cortex-A8 and an ARM Cortex-A9 processor designed around the OMAP5912, OMAP 3530 and OMAP4430 boards respectively. The efficiency and the accuracy of our proposed tool is evaluated by using a variety of basic programs to complex benchmarks. Estimated power values are compared to real board measurements for the different processor architecture based platforms. Our obtained power estimation results provid
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