This paper presents a new architecture for a 7-bit Binary to BCD (BD) converter which forms the core of our proposed high speed decimal Multi-operand Adder. Our proposed design contains various improvements over exist...
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This paper presents a new architecture for a 7-bit Binary to BCD (BD) converter which forms the core of our proposed high speed decimal Multi-operand Adder. Our proposed design contains various improvements over existing architectures. These include an improved 7-bit BD Converter that helps in reducing the delay of the Multi-operand decimal Adder. simulation results indicate that with a marginal increase in area, the proposed BD converter exhibits an improvement of 55% in delay and up to 27% reduction of power-delay product over earlier designs. Further the decimal Multi-operand Adder achieves up to 15% faster design and power-delay product falls to 13% when compared to previously published results.
Professional students are having experience of what they find more enjoyable in using Android games using internet and how they are learning through various application gives valuable information for the design of new...
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Professional students are having experience of what they find more enjoyable in using Android games using internet and how they are learning through various application gives valuable information for the design of new model intended for them. In this paper, we explore new concept consist of games application design model in E-learning cloud using Cloud as a medium to reach end user students. What will be outcomes in regard to the user interface and contents of the learning environments under E-learning cloud development. In Addition, we present importance related to designing new Games application model in E-learning cloud through simulation. So, we need to focus on what we want them to learn through games application. This gives is main concept of games application design model.
A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preem...
ISBN:
(纸本)9781479962778
A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preemptively target the concept design phase that determines 75% of a vehicle's cost. In our methodology, the marriage of systems engineering principles with high-level synthesis techniques results in a Functional modeling Compiler capable of generating high-fidelity simulation models for the design space exploration and validation of multiple cyber-physical (ECUs+Physics) vehicle architectures. Using real-world automotive use-cases, we demonstrate how functional models capturing cyber-physical aspects are synthesized into high-fidelity simulation models.
Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to suppo...
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Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to support the co-design and verification of such complex architectures including all its digital hardware/software and analog/multi-physical aspects using Multi-Disciplinary Virtual Prototyping (MDVP). Taking a Micro-Electro-Mechanical System (MEMS) vibration sensor as an example, we introduce a reusable framework based on the state-of-the-art technologies SystemC AMS, Finite Elements/Reduced-Order modeling, and UVM to design, simulate, and verify such systems in their real application context.
The simulation of aerospace vehicles is a challenging job as it consists of various expensive, fragile and unique subsystems. Apart from this, these systems are electrically connected and dynamically operated with the...
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The simulation of aerospace vehicles is a challenging job as it consists of various expensive, fragile and unique subsystems. Apart from this, these systems are electrically connected and dynamically operated with the state of the art simulation setup. The first release of the software embedded in them may not fulfil its complete requirements, which may lead to failure of subsystems. So simulation should be done at zero risk. Hence before connecting the hardware, all subsystems should be modelled in real time distributed environment. This paper describes the design and development of real time modelling and testing in distributed environment in cost effective manner for aerospace vehicle.
This paper studies the performance of battery models for hybrid electric vehicles (HEV). Two battery models are evaluated using plug-and-play powertrain and vehicle development software, Autonomie. The base vehicle mo...
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This paper studies the performance of battery models for hybrid electric vehicles (HEV). Two battery models are evaluated using plug-and-play powertrain and vehicle development software, Autonomie. The base vehicle model used for testing the performance of battery models is the Prius MY04, a power-split hybrid electric vehicle model in Autonomie. The battery model in Prius MY04 is based on the Thevenin battery model. It does not consider the effects of double layer, diffusion, and coulombs coefficient. To improve battery model, this study includes battery current loss in the battery model. In addition, voltage losses on double layer effect and diffusion effect are included in the improved battery model. simulation tests are conducted to compare simulated vehicle fuel economy with two battery models to the vehicle fuel economy test data provided by the department of energy (DOE). The simulation results show that the improved battery model has smaller fuel economy errors than the Thevenin battery model comparing with DOE published vehicle test data.
Particle advection is a foundational operation for many flow visualization techniques, including streamlines, Finite-Time Lyapunov Exponents (FTLE) calculation, and stream surfaces. The workload for particle advection...
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Particle advection is a foundational operation for many flow visualization techniques, including streamlines, Finite-Time Lyapunov Exponents (FTLE) calculation, and stream surfaces. The workload for particle advection problems varies greatly, including significant variation in computational requirements. With this study, we consider the performance impacts from hardware architecture on this problem, studying distributed-memory systems with CPUs with varying amounts of cores per node, and with nodes with one to three GPUs. Our goal was to explore which architectures were best suited to which workloads, and why. While the results of this study will help inform visualization scientists which architectures they should use when solving certain flow visualization problems, it is also informative for the larger HPC community, since many simulation codes will soon incorporate visualization via in situ techniques.
The following topics were dealt with: embedded parallel systems; network-on-a-chip; design space exploration; processor architecture; multiprocessors; reconfigurable computing; memory and caches.
The following topics were dealt with: embedded parallel systems; network-on-a-chip; design space exploration; processor architecture; multiprocessors; reconfigurable computing; memory and caches.
The proposed methodology is based on development of online algorithms for approximate solutions of the Hamilton-Jacobi-Bellman (HJB) equation through a family of non-squares approximators for critic adaptive solution ...
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The proposed methodology is based on development of online algorithms for approximate solutions of the Hamilton-Jacobi-Bellman (HJB) equation through a family of non-squares approximators for critic adaptive solution of the Discrete Algebraic Riccati Equation (DARE), associated with the problem of Discrete Linear Quadratic Regulator (DLQR). The proposed method is evaluated in a multivariable dynamic system of 4th order with two inputs and it is compared with standard recursive least square algorithm.
Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performa...
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Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performance metric that defines the extent to which a response is tied to a single device. It is often compromised if the manufacturing variations are suppressed. Though attempts have been made to improve the quality of a PUF at system level, very little work has been done at enhancing the impact of manufacturing variations on PUF circuits. In this work, we propose a novel generalized systematic framework for improving inter-die and inter-wafer manufacturing variations of a PUF circuit. The framework aligns the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. We validated the proposed technique using a large population sample of arbiter PUFs. simulation results show that the proposed scheme has improved inter-die and inter-wafer uniqueness of arbiter PUFs by as much as 8.4% and 16% respectively. The framework can be applied to any delay-based silicon PUF structure.
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