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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

On Manufacturing Aware Physical Design to Improve the Unique...

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international conference on VLSI Design

作者： Raghavan Kumar Siva Nishok Dhanuskodi Sandip Kundu Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performance metric that defines the extent to which a response is tied to a single device. It is often compromised if the manufacturing variations are suppressed. Though attempts have been made to improve the quality of a PUF at system level, very little work has been done at enhancing the impact of manufacturing variations on PUF circuits. In this work, we propose a novel generalized systematic framework for improving inter-die and inter-wafer manufacturing variations of a PUF circuit. The framework aligns the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. We validated the proposed technique using a large population sample of arbiter PUFs. simulation results show that the proposed scheme has improved inter-die and inter-wafer uniqueness of arbiter PUFs by as much as 8.4% and 16% respectively. The framework can be applied to any delay-based silicon PUF structure.

关键词： Integrated circuit modeling Logic gates Computational modeling Resists Manufacturing Semiconductor device modeling Systematics

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Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS

Forward Body Biased Adiabatic Logic for Peak and Average Pow...

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international conference on VLSI Design

作者： Matthew Morrison Nagarajan Ranganathan Department of Computer Science and Engineering University of South Florida Tampa Florida

Quantum mechanical principles that govern the basic laws of physics increasingly limit CMOS operation with transistor scaling. Traditional logic based CMOS circuits cannot achieve ultra-low power levels due to heat dissipated for a single bit loss of information as represented by the Landauer barrier. Reversible logic is a promising computing paradigm towards realization of ultra-low power computing circuits. Reducing average and peak power consumption is an effective strategy for mitigation of side-channel attacks, such as Differential Power Analysis. We present designs of Forward Body Biased Adiabatic Logic for reduction of average, peak, and differential power. HSPICE simulations with predictive 22nm technology are used to analyze performance metrics and exhaustive simulation results are presented for various reversible CMOS designs. Average power is improved upon by up to 91%, the peak power by up to 96%, and the differential power is improved by up to a factor of 128.57.

关键词： Logic gates Inverters CMOS integrated circuits Semiconductor device modeling Transistors Power demand Integrated circuit modeling

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Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications

Methodology of exploring ESL/RTL many-core platforms for dev...

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IEEE international SOC conference

作者： Jyu-Yuan Lai Chih-Tsun Huang Ting-Shuo Hsu Jing-Jia Liou Tung-Hua Yeh Liang-Chia Cheng Juin-Ming Lu Department of Computer Science National Tsing Hua University Hsinchu Taiwan Department of Electrical Engineering National Tsing Hua University Hsinchu Taiwan Information and Communications Research Laboratories Industrial Technology Research Institute Hsinchu Taiwan

Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as performance evaluation, speedup and bottleneck analysis, and system verification by taking the advantages of exploring many-core platforms in different abstraction levels altogether. To demonstrate our methodology, a design framework is proposed, consisting of a scalable many-core processor architecture and a hardware-independent software layer. Based on the scalable architecture, the prototype platform is also presented in Electronic System Level (ESL) and Register Transfer Level (RTL). The platform integrates sixteen Processing Elements (PEs) and a 4-by-4 mesh-based network with external memory. Our hardware-independent software layer aims at realistic parallel applications in the baremetal environment, i.e., without an Operating System (OS). With the on-chip communication library and system utilities, software built on top of the fast ESL many-core platform can be executed seamlessly on the RTL one. The analysis shows that our ESL simulation model provides relatively accurate performance metrics as compared with the RTL implementation, with up to 773.8 times faster in terms of simulation speed. In addition, we showcase the study of speedup and bottleneck analysis, which justifies the effectiveness of our methodology for embedded applications in many-core architectures.

关键词： Encoding Integrated circuit modeling Software Hardware Receivers Three-dimensional displays Transform coding

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TES-SAVi AWESUM™ model-based systems engineering (MBSE) for FACETM applications

TES-SAVi AWESUM™ model-based systems engineering (MBSE) for...

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IEEE conference on Aerospace

作者： Stephen M. Simi Sean P. Mulholland William G. Tanner Tucson Embedded Systems TES-SAVi A WESUM Tucson AZ

This paper presents an industry-unique approach and improved model-based engineering practices for software reliant aircraft systems aligned with the Future Airborne Capability Environment (FACE™) open system technical reference architecture. A lifecycle toolset is described which fuses systems and software modeling and simulation (M&S) capabilities, modular open system architectures (MOSA), and device and sensor integration techniques into a single package to enable rapid design, development, verification, certification, and deployment of interoperable, platform portable, embedded mission-critical safety-critical avionic systems. TES' MBSE lifecycle toolset, AWESUM™, supports system architecture and virtual integration (SAVI) of cyber-physical system (CPS) assets, and evaluation of these platform assets through simulated mission rehearsals in a network-centric collaborative virtual environment. The result is improved systems product. The toolset has been demonstrated to several aviation-focused communities including the American Helicopter Society international (AHS), the Association of Old Crows (AOC), the FACE Consortium, and the US Army's Aviation and Missile Research Development and Engineering Center (AMRDEC), with favorable response. TES demonstrated a virtual simulation of realistically modeled and simulated multiple dissimilar aircraft platform systems conducting network centric operations (NCO). With the goal of improving flight-safety and enhancing the situational awareness (SA) of the battle-space, virtual missions were executed showing the inter-operations of cyber-physical system (CPS) assets and capabilities from reusable FACE-aligned applications. The simulated battle-space was composed of device-configured simulated flight models of both manned and unmanned rotorcraft platforms operating within a virtual environment of real-world terrain data. The environment included simulated threats and obstacles used to stimulate platform devices that report det

关键词： Atmospheric modeling Data models Software Object oriented modeling Standards

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Power optimized high level synthesis of Multiply-and-Accumulate (MAC) based digital filter architectures under SNR constraints

Power optimized high level synthesis of Multiply-and-Accumul...

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international conference on Information Communication and embedded systems (ICICES)

作者： N. Alivelu Manga M. Madhavi Latha Dept. of ECE CBIT Hyderabad Andhra Pradesh India Dept of ECE JNTUH Hyderabad Andhra Pradesh India

The optimum word length selection for arithmetic circuits in VLSI implementation is crucial in optimizing the design for area and power. This paper proposes a scheme for further word length optimization (WLO) using system level parameters such as dynamic range and SNR. A scaled fixed point (SFXP) representation is discussed, which has advantages of both fixed point and floating point. The dynamic range and noise aspects of chosen representation are simulated using MATLAB. The results show only 1 dB SNR degradation for signals with SNR of 17 dB, when a 15 bit ADC output is represented with (3,4) SFXP representation. To illustrate the suitability of the proposed WLO scheme under practical signal conditions, a Multiply-and-Accumulate (MAC) unit is realized with SFXP representation for simulation and synthesis studies. Power saving up to 20% is observed for Xilinx's Spartan 6 FPGAs, in comparison with conventional MAC implementation. Algorithm for high level synthesis (HLS) of MAC units from signal flow graph (SFG) with proposed SFXP representation is presented.

关键词： Signal to noise ratio Finite impulse response filters Optimization computer architecture Dynamic range Receivers

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Modelling and Stochastic simulation of Synthetic Biological Boolean Gates

Modelling and Stochastic Simulation of Synthetic Biological ...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Daven Sanassy Harold Fellermann Natalio Krasnogor Savas Konur Laurentiu M. Mierla Marian Gheorghe Christophe Ladroue Sara Kalvala School of Computing Science Newcastle University Newcastle Upon Tyne UK School of Computer Science University of Sheffield Sheffield UK School of Computer Science University of Warwick Coventry UK

Synthetic Biology aspires to design, compose and engineer biological systems that implement specified behaviour. When designing such systems, hypothesis testing via computational modelling and simulation is vital in order to reduce the need of costly wet lab experiments. As a case study, we discuss the use of computational modelling and stochastic simulation for engineered genetic circuits that implement Boolean AND and OR gates that have been reported in the literature. We present performance analysis results for nine different state-of-the-art stochastic simulation algorithms and analyse the dynamic behaviour of the proposed gates. Stochastic simulations verify the desired functioning of the proposed gate designs.

关键词： Computational modeling Logic gates Biological system modeling Stochastic processes Genetics Mathematical model Integrated circuit modeling

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CryptIP: An Approach for Encrypting Intellectual Property Cores with simulation Capabilities

CryptIP: An Approach for Encrypting Intellectual Property Co...

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international conference on VLSI Design

作者： Spencer Millican Parameswaran Ramanathan Kewal Saluja Department of Electrical and Computer Engineering University of Wisconsin-Madison Madison WI

Modern complex digital designs are becoming feasible due to the use of System on Chip design techniques in which designers use Intellectual Property (IP) cores and their own glue logic to create a design. A major limitation in testing such designs is that the designer is restricted to use the test vectors provided by the IP core provider. For a designer to use their own test vectors, the designer must have full gate level access, not just the functional access, to the implementation of the IP core. IP providers are often reluctant to provide such access for proprietary reasons. This paper proposes a method of encrypting a logic circuit such that the structural information of the design is preserved but the gate/component functionalities are encrypted. The encryption is such that a designer can perform logic as well as fault simulation on the encrypted circuit without deducing the gate/component functionalities of the gates/components in the circuit. This gives the designer the capability to design the logic around the IP core as well as use its own test vectors and to target desired fault coverage. The details of the encryption method and the complexity of decryption are discussed in the paper. The paper also shows how logic and fault simulation can be performed on the encrypted circuit and the performance of such simulation is comparable to simulating the un-encrypted circuit.

关键词： Circuit faults Logic gates IP networks Integrated circuit modeling Encryption System-on-chip

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RLS Algorithms and Convergence Analysis Method for Online DLQR Control Design via Heuristic Dynamic Programming

RLS Algorithms and Convergence Analysis Method for Online DL...

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international conference on computer modeling and simulation, UKSIM

作者： Watson R.M. Santos Jonathan A. Queiroz João Viana da F. Neto Patrícia H. M. Rêgo Ewaldo Santana Gustavo Andrade Federal University of Maranhão Embedded Systems and Intelligent Control Laboratory São Luis Maranhão Brazil

In this paper, a method to design online optimal policies that encompasses Hamilton-Jacobi-Bellman (HJB) equation solution approximation and heuristic dynamic programming (HDP) approach is proposed. Recursive least squares (RLS) algorithms are developed to approximate the HJB equation solution that is supported by a sequence of greedy policies. The proposal investigates the convergence properties of a family of RLS algorithms and its numerical complexity in the context of reinforcement learning and optimal control. The algorithms are computationally evaluated in an electric circuit model that represents an MIMO dynamic system. The results presented herein emphasize the convergence behaviour of the RLS, projection and Kaczmarz algorithms that are developed for online applications.

关键词： Equations Mathematical model Least squares approximations Heuristic algorithms Approximation algorithms Convergence

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PowerCool: simulation of integrated microfluidic power generation in bright silicon MPSoCs

PowerCool: Simulation of integrated microfluidic power gener...

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IEEE international conference on computer-Aided Design

作者： Arvind Sridhar Mohamed M. Sabry Patrick Ruch David Atienza Bruno Michel IBM Research Zurich Embedded Systems Lab (ESL) EPFL Lausanne

Integrated microfluidic power generation and power delivery promises to be a disruptive packaging technology with the potential to combat dark silicon. It essentially consists of integrated microchannel-based electrochemical “flow cells” in a 2D/3D multiprocessor system-on-chip (MPSoC), that generate electricity to power up the entire or part of the chip, while also simultaneously acting as a high-efficiency microfluidic heat sink. Further development of this technology requires efficient modeling tools that would assess the efficacy of such solutions and help perform early-stage design space exploration. In this paper, we propose a compact mathematical model, called PowerCool, that performs electro-chemical modeling and simulation of integrated microfluidic power generation in MPSoCs. The accuracy of the model has been validated against fine-grained multiphysics simulations of flow cells in the COMSOL software that is unsuitable for EDA because of large simulation times. PowerCool model is demonstrated to be up to 425x times faster than COMSOL simulations while incurring a worst-case error of only 5%. Furthermore, the PowerCool model has been used to study and assess the efficacy of this technology for a test MPSoC.

关键词： Mathematical model Microchannels Electric potential Cathodes Anodes Equations

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modeling and identification of a fractional-order discrete-time SISO Laguerre-Wiener system

Modeling and identification of a fractional-order discrete-t...

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international conference on Methods and Models in Automation and Robotics (MMAR)

作者： Rafal Stanisławski Krzysztof J. Latawiec Marcin Gałek Marian Łukaniszyn Department of Electrical Control and Computer Engineering Opole University of Technology Opole Poland

This paper presents a new implementable strategy for modeling and identification of a fractional-order discrete-time nonlinear block-oriented SISO Wiener system. The concept of modeling of a linear dynamics by means of orthonormal basis functions (OBF) is employed to separate linear and nonlinear submodels, which enables a linear regression formulation of the parameter estimation problem. Finally, discrete-time Laguerre filters are uniquely embedded in modeling of the fractional-order dynamics, eliminating the disastrous bilinearity issue. simulation experiments show a very good identification performance for a fractional-order Laguerre-based Wiener model, both in terms of low prediction errors and accurate reconstruction of the actual system characteristics.

关键词： Computational modeling Mathematical model Nonlinear dynamical systems Predictive models Adaptation models Stability analysis Approximation methods

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