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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications

Implementation of fast multiplier using modified Radix-4 boo...

引用

international conference on Computational systems and Communications (ICCSC)

作者： E K Laya Surendran P Rony Antony Rajagiri School of Engineering and Technology Ernakulam Kerala IN

The main objective of this paper is to implement a multiplier for high speed and low energy applications. Multipliers are the building blocks of high performance systems like FIR filters, Digital signal processors, etc in which speed is the dominating factor. There are many multiplier architectures developed to increase the speed of algebra. Booth algorithm is the most effective algorithm used for fast performances. This works by introducing a high performance multiplier using Modified Radix-4 booth algorithm with Redundant Binary Adder to get high speed. A comparative study of different booth algorithms in terms of power consumption, delay, area, energy and energy delay product is also discussed in this work. All the circuits are simulated in the Cadence simulation tool using 180nm technology. The experimental results show that the proposed booth multiplier shows high speed, low energy and low energy delay product compared to the existing booth multipliers.

关键词： Adders Delays Signal processing algorithms Generators computer architecture Power demand Integrated circuit modeling

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An FPGA-based development platform for real-time solid state devices

An FPGA-based development platform for real-time solid state...

引用

international conference on Information Science, Electronics and Electrical Engineering (ISEEE)

作者： Muhammed Ziya Komsul Alistair A. McEwan Irfan F. Mir Department of Engineering University of Leicester Leicester UK

NAND flash-based Solid State Devices (SSD) are widely used in embedded applications because of their low power consumption, high performance, and shock resistant features. However, these devices have non-deterministic response times due to erase-before-write requirements of NAND flash memory. This is a problem for applications that require real-time access to data storage facilities. Recent work has investigated novel RAID-based architectures for highly reliable SSD storage systems, with the host interface, controller, and other facilities such as garbage collectors implemented on an FPGA. The architecture gives high reliability and guarantees of data integrity in a way that protects against the known failure characteristics of flash memory, but at a further expense of timing guarantees. The contribution of this paper is the presentation, design, and analysis of a co-design simulation platform implemented in a PowerPC based FPGA environment that allows us to investigate the timing constraint issues that result from our architecture.

关键词： Hardware Real-time systems Software Ash computer architecture Reliability Field programmable gate arrays

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Specification and modeling of QoS Based on AADL

Specification and Modeling of QoS Based on AADL

引用

2014 IEEE 5th international conference on Software Engineering and Service Science

作者： Lichen Zhang Faculty of Computer Science and Technology Guangdong University of Technology Shanghai Key Laboratory of Trustworthy Computing East China Normal University

Specifying and modeling Quality of Service(QoS) properties represents a key challenge for cyber physical system *** of Service(QoS) is a general term that specifies system quality and performance,as opposed to system functionality of cyber physical *** specification is concerned with capturing application level QoS requirements and management policies of cyber physical *** Analysis and Design Language(AADL) is a textual and graphic language used to design and analyze the software and hardware architectures of embedded and realtime systems for performance-critical characteristics(e.g.,endto-end latency,schedulability,and reliability),AADL supports the representation of end-to-end flows through the concept of a flow specification This paper proposes an approach to specify and model QoS based on *** present our current effort to apply and extend AADL to specify and model QoS of cyber physical systems,finally,we illustrate QoS specifying and modeling via an example of specifying and modeling Vehicular Ad-hoc NETwork(VANET).

关键词： QoS cyber physical systems aspect-oriented AADL

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FlexCore: Implementing an Exposed Datapath Processor

FlexCore: Implementing an Exposed Datapath Processor

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Sjaelander, Magnus Larsson-Edefors, Per Florida State Univ Dept Comp Sci Tallahassee FL 32306 USA Chalmers Univ Technol Dept Comp Sci & Engn S-41296 Gothenburg Sweden

ISBN: (纸本)9781479901036

The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualized in the FlexSoC programme. By way of a crossbar switch interconnect, all execution units in a FlexCore datapath can potentially communicate, allowing the inherent hardware parallelism to be utilized. This interconnect enables configuration of a datapath to match an application domain, for example, by way of datapath accelerators. The baseline FlexCore is a general-purpose processor (GPP) and since all FlexCore configurations are extensions to the baseline, they offer GPP functionality as complement to the domain-specific functionality. This paper gives an overview of the implementation of complete FlexCore processors, accompanied with discussions on datapath interconnects, datapath extensions and instruction decompression.

关键词： multiprocessor interconnection networks parallel architectures

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TimeCube: A Manycore embedded Processor with Interference-Agnostic Progress Tracking

TimeCube: A Manycore Embedded Processor with Interference-Ag...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Gupta, Anshuman Sampson, Jack Taylor, Michael Bedford Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781479901036

Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. This decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing. In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6x average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.

关键词： cloud computing embedded systems interference microprocessor chips multiprocessing systems resource allocation

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OpenCL Code Generation for Low Energy Wide SIMD architectures with Explicit Datapath

OpenCL Code Generation for Low Energy Wide SIMD Architecture...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： She, Dongrui He, Yifan Waeijen, Luc Corporaal, Henk Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781479901036

Energy efficiency is one of the most important aspects in designing embedded processors. The use of a wide SIMD processor architecture is a promising approach to build energy-efficient high performance embedded processors. In this paper, we propose a configurable wide SIMD architecture that utilizes explicit datapath to achieve high energy efficiency. To efficiently program the proposed architecture with a standard parallel programming language, we introduce a toolflow that can compile and map OpenCL programs onto it. The compiler in the proposed toolflow is able to analyze the static access patterns in OpenCL kernels and generate efficient mapping and code that utilizes the explicit datapath. Experimental results show that the proposed architecture is efficient. In a 128-PE processor, the proposed architecture is able to achieve over 200 times speed-up and reduce the energy consumption of register file and memory by over 90% compared to a RISC processor.

关键词： Wide SIMD Explicit Datapath Low Power OpenCL Code Generation

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Deploying OpenMP on an embedded Multicore Accelerator

Deploying OpenMP on an Embedded Multicore Accelerator

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Agathos, Spiros N. Dimakopoulos, Vassilios V. Mourelis, Aggelos Papadogiannakis, Alexandros Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece

ISBN: (纸本)9781479901036

Multiprocessor systems-on-chip (MPSoC) are now considered first-class citizens both in the embedded systems and in the high-performance computing arenas, in the form of specialized or general-purpose accelerators. Programming models for such systems is currently a hot research topic, and as a general rule require deep programmer knowledge of the underlying hardware architecture. In this paper we present the implementation of OpenMP, one of the most intuitive and productive programming models, on the STHORM accelerator. This particular platform provides a shared-memory substrate which OpenMP requires. An innovative feature of our design is the deployment of the OpenMP model both at the host and the fabric sides, in a seamless way, which provides the programmer with a simple but effective interface for offloading and executing OpenMP kernels on the MPSoC. The optimized runtime environment provides full OpenMP support despite its small footprint (less than 10KB for a 16-core cluster) and can sustain close-to-ideal speedups in computationally intensive applications. We detail on design issues we faced along with their solutions, given the limited available resources.

关键词： embedded systems multiprocessing systems shared memory systems system-on-chip

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Low-Power Application-Specific FFT Processor for LTE Applications

Low-Power Application-Specific FFT Processor for LTE Applica...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Patyk, Tomasz Guevorkian, David Pitkanen, Teemu Jaaskelainen, Pekka Takala, Jarmo Dolby Labs Wroclaw Poland Nokia Siemens Networks Espoo Finland Tampere Univ Technol FIN-33101 Tampere Finland

ISBN: (纸本)9781479901036

In this paper, we describe a processor architecture tailored to mixed-radix4/2/3 FFT algorithm. The proposed design supports all FFT sizes, namely 128-2048/1536, required by the LTE applications. The processor is based on the Transport Triggered Architecture processor architecture, which was customized with a set of function units, designed especially for the application at hand. The processor has been synthesized on an ASIC technology and both energy-efficiency and performance have been evaluated. The developed processor is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.

关键词： Fast Fourier Transform Long-Term Evolution Application-Specific Integrated Circuit Parallel architectures

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modeling Pipelined Application with Synchronous Data Flow Graphs

Modeling Pipelined Application with Synchronous Data Flow Gr...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Lattuada, Marco Ferrandi, Fabrizio Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20133 Milan Italy

ISBN: (纸本)9781479901036

Streaming applications can efficiently exploit multiprocessors architectures by means of pipelined parallelism, but designing this type of applications can be an hard task. Different subproblems have indeed to be solved: partitioning, mapping, scheduling and pipeline stage assignment. For this reason, high level abstraction models are adopted during design flow since they simplify this process by hiding most of the architectural details. Synchronous Data Flow (SDF) graphs, widely adopted to describe streaming applications, naturally model only their partitioning, so they usually have to be integrated with other types of representations. In this paper Pipelined Application modeling (PAM), a methodology to create a Synchronous Data Flow graph describing all the aspects of a pipelined application, is presented. The methodology starts from the SDF graph describing the partitioning of the application and enriches it with new actors and channels detailing the mapping, the scheduling and the pipeline stage assignment of the considered solution. The obtained SDF graph, describing all the aspects of the solution in a formal and compact way, facilitates the evaluation of different solutions during design space exploration.

关键词： data flow graphs multiprocessing systems pipeline processing

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Parallel Implementation of Real-Time Semi-Global Matching on embedded Multi-Core architectures

Parallel Implementation of Real-Time Semi-Global Matching on...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Banz, Christian Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Corporate Techn D-81739 Munich Germany

ISBN: (纸本)9781479901036

embedded real-time algorithms are often realized with dedicated hardware, exhibiting high production costs and low programming flexibility thereafter. For instance, semi-global matching for stereo image processing, including complex data flows, traditionally runs on customized hardware modules. Combining the processing and memory capabilities of multiple individual cores, emerging embedded multi-core technologies address these problems. However, considering concurrency issues (e. g., data races and lock contentions), parallel programming requires experienced programmers and technology-specific techniques (e. g., synchronization libraries) and tools (e. g., parallel profilers), which are often not available on embedded platforms. In this work, we introduce a parallel version of a semi-global matching algorithm and demonstrate within this case study runtime optimizations necessary to meet real-time requirements. We also show structured steps of the applied parallelization workflow, illustrating an efficient migration strategy to multi-core platforms using runtime information (e. g., profiles and hardware counters). Finally, to evaluate the resulting performance characteristics, we compare the runtime behavior of the parallel version running on a Freescale P4080 processor with reference values taken on an Intel i7, a field-programmable logic device, an extended general purpose processor and a GPU.

关键词： concurrency control embedded systems image matching multiprocessing systems parallel architectures parallel programming performance evaluation

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