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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Design of a Unified Transport Triggered Processor for LDPC/Turbo Decoder

Design of a Unified Transport Triggered Processor for LDPC/T...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Shahabuddin, Shahriar Janhunen, Janne Bayramoglu, Muhammet Fatih Juntti, Markku Ghazi, Amanullah Silven, Olli Univ Oulu Dept Commun Engn SF-90100 Oulu Finland Univ Oulu Dept Comp Sci & Engn SF-90100 Oulu Finland

ISBN: (纸本)9781479901036

This paper summarizes the design of a programmable processor with transport triggered architecture (TTA) for decoding LDPC and turbo codes. The processor architecture is designed in such a manner that it can be programmed for LDPC or turbo decoding for the purpose of internetworking and roaming between different networks. The standard trellis based maximum a posteriori (MAP) algorithm is used for turbo decoding. Unlike most other implementations, a supercode based sum-product algorithm is used for the check node message computation for LDPC decoding. This approach ensures the highest hardware utilization of the processor architecture for the two different algorithms. Up to our knowledge, this is the first attempt to design a TTA processor for the LDPC decoder. The processor is programmed with a high level language to meet the time-to-market requirement. The optimization techniques and the usage of the function units for both algorithms are explained in detail. The processor achieves 22.64 Mbps throughput for turbo decoding with a single iteration and 10.12 Mbps throughput for LDPC decoding with five iterations for a clock frequency of 200 MHz.

关键词： computer architecture maximum likelihood estimation optimisation parity check codes turbo codes

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Source Code Annotated Memory Leak Detection for Soft Real Time embedded systems with Resource Constraints

Source Code Annotated Memory Leak Detection for Soft Real Ti...

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IEEE international Symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Mabel Mary Joy Wolfgang Mueller Franz Josef Rammig C-Lab University of Paderborn Germany Heinz Nixdorf Institute University of Paderborn Germany

With ever increasing complexity of software and increased competition in the market, it is very important to minimize the production to market delivery time. Early phase detection of serious errors in the design and program can be done with automated approaches which save time. Memory leaks are the most important memory related problems which are severe threats to software applications. We propose a novel hybrid automated source code annotated memory leak detection approach for soft real time embedded system software with no garbage collection. We utilize our source code annotation tool to detect the potential memory leak candidates, which are further analyzed in our hybrid leak detection approach. The control flow graph of the source code generated with our annotation tool provides information of all execution paths, where the basic blocks are annotated with specific marks. Our hybrid method combines static and dynamic approaches. Static phase of the hybrid approach detect the potential leak candidates from the control flow graph. Dynamic phase filters false positives from the static phase results and provide results on the actual leaks. In early design stages where a real execution environment and complete executable software are unavailable, a simulation environment and a virtual platform are necessary. Virtual platforms provide flexibility to change the target architecture to be tested. Our proposed dynamic phase of the approach runs on the virtual memory model platform we implemented in SystemC at an abstract level using Transaction Level modeling. The software under test is run on top of this model. This makes our approach faster and provides early results. Our approach can be easily deployed across a variety of architectures as it is compiler independent and does not implement any architecture specific features. Moreover the automated approach provides an efficient methodology to determine potential leaks in early phases of software development.

关键词： Leak detection Software Memory management Resource management Real-time systems Pattern matching

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Energy-delay tradeoffs of virtual base stations with a computational-resource-aware energy consumption model

Energy-delay tradeoffs of virtual base stations with a compu...

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international conference on Communication systems

作者： Tao Zhao Jian Wu Sheng Zhou Zhisheng Niu Department of Electronic Engineering Tsinghua University Beijing China

ISBN: (纸本)9781479958337

The next generation (5G) cellular network faces the challenges of efficiency, flexibility, and sustainability to support data traffic in the mobile Internet era. To tackle these challenges, cloud-based cellular architectures have been proposed where virtual base stations (VBSs) play a key role. VBSs bring further energy savings but also demands a new energy consumption model as well as the optimization of computational resources. This paper studies the energy-delay tradeoffs of VBSs with delay tolerant traffic. We propose a computational-resource-aware energy consumption model to capture the total energy consumption of a VBS and reflect the dynamic allocation of computational resources including the number of CPU cores and the CPU speed. Based on the model, we analyze the energy-delay tradeoffs of a VBS considering BS sleeping and state switching cost to minimize the weighted sum of power consumption and average delay. We derive the explicit form of the optimal data transmission rate and find the condition under which the energy optimal rate exists and is unique. Opportunities to reduce the average delay and achieve energy savings simultaneously are observed. We further propose an efficient algorithm to jointly optimize the data rate and the number of CPU cores. Numerical results validate our theoretical analyses and under a typical simulation setting we find more than 60% energy savings can be achieved by VBSs compared with conventional base stations under the EARTH model, which demonstrates the great potential of VBSs in 5G cellular systems.

关键词： Power demand Computational modeling Delays Energy consumption computer architecture Analytical models Earth

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An embedded Hardware-Efficient Architecture for Real-Time Cascade Support Vector Machine Classification

An Embedded Hardware-Efficient Architecture for Real-Time Ca...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Kyrkou, Christos Theocharides, Theocharis Bouganis, Christos-Savvas Univ Cyprus KIOS Res Ctr Dept Elect & Comp Engn Nicosia Cyprus Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781479901036

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640x480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5x over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.

关键词： Field Programmable Gate Arrays Support Vector Machines Cascade Classifier Real-time and embedded systems Parallel Architecture

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Energy-Aware-Task-Parallelism for Efficient Dynamic Voltage, and Frequency Scaling, in CGRAs

Energy-Aware-Task-Parallelism for Efficient Dynamic Voltage,...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Jafri, Syed. M. A. H. Tajammul, Muhammad Adeel Hemani, Ahmed Paul, Kolin Plosila, Juha Tenhunen, Hannu Royal Inst Technol Stockholm Sweden Turku Univ Turku Finland Indian Inst Technol Delhi India Turku Ctr Comp Sci Turku Finland

ISBN: (纸本)9781479901036

Today, coarse grained reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Each application itself is composed of multiple tasks, spatially mapped to different parts of platform. Providing worst-case operating point to all applications leads to excessive energy and power consumption. To cater this problem, dynamic voltage and frequency scaling (DVFS) is a frequently used technique. DVFS allows to scale the voltage and/or frequency of the device, based on runtime constraints. Recent research suggests that the efficiency of DVFS can be significantly enhanced by combining dynamic parallelism with DVFS. The proposed methods exploit the speedup induced by parallelism to allow aggressive frequency and voltage scaling. These techniques, employ greedy algorithm, that blindly parallelizes a task whenever required resources are available. Therefore, it is likely to parallelize a task(s) even if it offers no speedup to the application, thereby undermining the effectiveness of parallelism. As a solution to this problem, we present energy aware task parallelism. Our solution relies on a resource allocation graphs and an autonomous parallelism, voltage, and frequency selection algorithm. Using resource allocation graph, as a guide, the autonomous parallelism, voltage, and frequency selection algorithm parallelizes a task only if its parallel version reduces overall application execution time. simulation results, using representative applications (MPEG4, WLAN), show that our solution promises better resource utilization, compared to greedy algorithm. Synthesis results (using WLAN) confirm a significant reduction in energy (up to 36%), power (up to 28%), and configuration memory requirements (up to 36%), compared to state of the art.

关键词： greedy algorithms power aware computing reconfigurable architectures resource allocation wireless LAN

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Parallelizing General Histogram Application for CUDA architectures

Parallelizing General Histogram Application for CUDA Archite...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Milic, Ugljesa Gelado, Isaac Puzovic, Nikola Ramirez, Alex Tomasevic, Milo Ctr Nacl Supercomputac Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain Univ Belgrade Sch Elect Engn YU-11001 Belgrade Serbia

ISBN: (纸本)9781479901036

Histogramming is a tool commonly used in data analysis. Although its serial version is simple to implement, providing an efficient and scalable way to parallelize it can be challenging. This especially holds in case of platforms that contain one or several massively parallel devices like CUDA-capable GPUs due to issues with domain decomposition, use of global memory and similar. In this paper we compare two approaches for implementing general purpose histogramming on GPUs. The first algorithm is based on private copies of bin counters stored in shared memory for each block of threads. The second one uses the Thrust library to sort the input elements and then to search for upper bounds according to bin widths. For both algorithms we analyze how the speedup over the sequential version depends on the size of input collection, number of bins, and the type and distribution of input elements. We also implement overlapping of data transfers between host CPU and CUDA device with kernel execution. For both algorithms we analyze the pros and cons in detail. For example, privatization strategy can be up to 2x faster than sort-search with realistic inputs, but can only support a limited number of bins. On the other hand, sort-search strategy has about 50% higher speedup than privatization when we use characters as input and can support unlimited number of bins. Finally, we perform an exploration to determine the optimal algorithm depending on the characteristics and values of input parameters.

关键词： data analysis graphics processing units parallel architectures shared memory systems

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Emergence of Cooperation in Competitive Environments

Emergence of Cooperation in Competitive Environments

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international IEEE conference on Signal-Image Technologies and Internet-Based System

作者： Marco Alberto Javarone Antonio Emanuele Atzeni Dept. of Mathematics and Computer Science University of Cagliari Cagliari Italy Dept. of Physics University of Cagliari Cagliari Italy

We study the Prisoner's Dilemma in competitive environments with the aim to investigate if, and under which conditions, a cooperative behavior emerges in an agent population. In particular, agents are embedded in two different regions of space, i.e., A continuous space and a discrete space. The former is represented by a simple square, whereas the latter by a directed network. In both spaces, agents face by playing the Prisoner's Dilemma with their neighbors. In the continuous space, neighbors are identified by a rule based on the Euclidean distance among agents. Instead, in the network, agents have as neighbors those connected with them. In the proposed model, the competitiveness corresponds to the number of opponents each agent decides to face, i.e., Competitive agents faces many agents at each time step. Therefore, in the continuous space, the competitiveness is represented by the radius of each agent within it finds its opponents. Instead, in the discrete space, the competitiveness corresponds to the agent's out-degree, i.e., The number of neighbors connected with an arrow starting from the considered agent an directed to its neighbors. We study the evolution of the system over time in both spaces, analyzing also the degree distribution (both the in-degree and the out-degree) of the resulting directed network. It is worth to highlight that, as main result, we found the competitiveness strongly improves cooperation among agents in both domains. Furthermore, as cooperation emerges when the Prisoner's Dilemma is played over a network, several agents become hubs (i.e., Agents with a high out-degree).

关键词： Face Numerical models Games Sociology Statistics Numerical simulation Computational modeling

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A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained Reconfigurable architectures

A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained ...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Ferreira, Ricardo Duarte, Vinicius Meireles, Waldir Pereira, Monica Carro, Luigi Wong, Stephan Univ Fed Vicosa Dept Informat BR-36570000 Vicosa MG Brazil Univ Fed Rio Grande do Norte DIMAP BR-59078970 Natal RN Brazil Univ Fed Rio Grande do Sul BR-91501970 Porto Alegre RS Brazil Delft Univ Technol EEMCS Dept Comp Engn NL-2600 GA Delft Netherlands

ISBN: (纸本)9781479901036

In the past decade, most solutions concerning the mapping of the compute-intensive loop kernels to accelerators have used heuristics and compiler-based strategies. These facts require that most of the decisions be taken at design time, thus precluding efficient solutions that can take run-time information into account. Any success in accelerating such applications greatly depends on two steps, extracting the loops and mapping them into the architecture. This last step is a challenge in itself since it is a NP-complete problem. In this paper, we propose a runtime solution that can provide speed ups of 3 to 6 orders of magnitude for the mapping step when compared to the state-of-the-art at minimal performance degradation, by the combined usage of 3 distinct mechanisms: 1) a simple and efficient modulo scheduling heuristic, 2) a crossbar network, which simplifies the placement and routing, 3) a virtual coarse-grained reconfigurable architecture (CGRA). Additionally, since the CGRA is a virtual layer on top of an FPGA, it is possible to use any off-the-shelf FPGA without the need of special tools or IP solutions. Although the mapping is NP-complete even for crossbar-based CGRAs, experimental results demonstrate a huge reduction in compilation time, as opposed to previous solutions that require seconds to map the applications, our solution requires only microseconds to find near optimal schedules. Besides the speed up, the proposed solution enables the use of just-in-time compilation, hence it is intrinsically adaptive to a changing scenario.

关键词： computational complexity field programmable gate arrays processor scheduling reconfigurable architectures

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Virtual prototyping of multiprocessor architectures using the Open Virtual Platform

Virtual prototyping of multiprocessor architectures using th...

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international conference on computer Applications Technology (ICCAT)

作者： Rekik, Wijdene Ben Said, Mouna Ben Amor, Nader Abid, Mohamed Univ Sfax ENIS CES Lab Sfax Tunisia

ISBN: (纸本)9781467352857

The complexity of System on Chip (SoC) design is increasing continuously with the use of MultiProcessor System on Chip (MPSoC) architectures. Mastering the complexity of these systems with a typical co-design workflow is really recommended. As such, computer aided design tools are needed to alleviate the task of designers. There is a lack of co-design tools that support multiprocessor architectures with Operating System (OS) support. Virtual platforms enable us to discover the interactive design space exploration at early stage in the design. They make designing embedded systems less tedious and elevate the low technical details to manage systems complexity and reduce time to market. In this paper, we present an exploration of the Open Virtual Platform (OVP) capabilities for multiprocessor architectures simulation. We particularly focus on the inter-processor communication facilities. We illustrate this study by a set of homogeneous and heterogeneous multiprocessor architectures with different memory hierarchies and peripherals followed by a run of several applications. We also integrate the use of OS to permit workload distribution among processors using several case studies to validate our system.

关键词： Open Virtual Platform(OVP) multiprocessor homogeneous heterogeneous Operating System(OS) System on Chip(SoC)

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modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation

Modeling and FPGA implementation of reconfigurable transcode...

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2013 IEEE international conference on Electronics, Circuits, and systems

作者： Dabellani, Eric Rabah, Hassan Marques, Nicolas Berviller, Yves Jovanovic, Slavisa Weber, Serge Univ Lorraine UMR7198 JIL F-54000 Nancy France

ISBN: (纸本)9781479924523

Video adaption is one of the main solutions to offer access to the large array of existing multimedia contents and the variety of terminals and networks. This adaptation can be achieved efficiently using transcoding techniques. The implementation of the various adaptation possibilities and techniques in embedded systems such as home gateway requires flexible and efficient architectures. This paper presents a hardware reconfigurable architecture for the real time adaptation of video contents for different terminals and available bandwidth. This architecture is designed to adapt a compressed stream in advanced video coding standard (H264/AVC) and/or MPEG-2. A system level model of reconfigurable transcoder is developed for IP integration and architectural exploration by taking into account dynamic and partial reconfiguration. The developed simulation model of dynamic partial reconfiguration allowed the early estimation of performances and the design of the suitable solution for the considered transcoding scenarios.

关键词： Reconfigurable architectures

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