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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy

SWAN-iCare: A smart wearable and autonomous negative pressur...

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Texier, Isabelle Marcoux, Pierre Pham, Pascale Muller, Marie Benhamou, Pierre-Yves Correvon, Marc Dudnik, Gabriela Voirin, Guy Bue, Natascha Cristensen, Jan Laurenza, Massimo Gazzara, Giuseppe Raptopoulos, Andreas Bartzas, Alex Soudris, Dimitrios Saxby, Carl Navarro, Thierry di Francesco, Fabio Salvo, Pietro Romanelli, Marco Paggi, Battistino Lymperopoulos, Leonidas CEA Leti MINATEC Campus17 Rue Martyrs F-38054 Grenoble 9 France CHU Grenoble Clinique Endocrinol Diabetol Pole DigiDune F-38043 Grenoble France Ctr Suisse Elect & Microtech CH-2002 Neuchatel Switzerland European Wound Management Assoc DK-2000 Frederiksberg Denmark Eurores I-20122 Milan Italy EXUS Athens GR-11526 Greece Haemopharm Biofluids I-20122 Milan Italy Natl Tech Univ Athens ICCS Sch Elect & Comp Engn Athens Greece Smith & Nephew Wound Management Kingston Upon Hull HU3 2BN N Humberside England Swissinnov CH-1196 Gland Switzerland Univ Pisa Dipartimento Chim & Chim Ind I-56126 Pisa Italy Univ Pisa Wound Healing Res Unit I-56126 Pisa Italy

ISBN: (纸本)9781479901036

The EU FP7 SWAN-iCare project aims at developing an integrated autonomous device for the monitoring and the personalized management of chronic wounds, mainly diabetic foot ulcers and venous leg ulcers. Most foot and leg ulcers are caused by diabetes and vascular problems respectively but a remarkable number of them are also due to the co-morbidity influence of many other diseases (e. g. kidney disease, congestive heart failure, high blood pressure, inflammatory bowel disease). More than 10 million people in Europe suffer from chronic wounds, a number which is expected to grow due to the aging of the population. The core of the project is the fabrication of a conceptually new wearable negative pressure device equipped with Information and Communication Technologies. Such device will allow users to: (a) accurately monitor many wound parameters via non-invasive integrated micro-sensors, (b) early identify infections and (c) remotely provide an innovative personalized two-line therapy via non-invasive micro-actuators to supplement the negative pressure wound therapy. This paper describes the main components of the SWAN-iCare system and its potential impact in the area of wound management.

关键词： SWAN-iCare wound monitoring sensors actuators medical software embedded software

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SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory systems

SmartMig: A Case for Page Migration and Self-Interleaving fo...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Weiwei Fu Mingmin Yuan Tianzhou Chen Qingsong Shi Li Liu Minghui Wu College of Computer Science Zhejiang University Hangzhou Zhejiang P.R. China School of Information Zhejiang Sci-Tech University Hangzhou Zhejiang P.R. China City College Zhejiang University Hangzhou Zhejiang P.R. China

ISBN: (纸本)9781479961245

This paper tries to optimize the placements of data pages, which have a strong impact on system performance. We find that both core-to-memory distance and contention on MCs and interconnects are critical. Migrating pages to their page access center can mini-mize average memory access distance, but may cause serious contention and congestion, necessitating further schemes for load balancing. Based on these observations, we propose a novel runtime mechanism called SmartMig, in which we mi-grate data pages to shorten memory access distance, while employ page self-interleaving to balance the load across the nodes. We propose models and algorithms to decide the fate of candidate pages. simulation results show that SmartMig achieves performance improvements by 26.9% and 21.0% in terms of normalized IPC and average memory access latency, which is a result of significant reduction of core-to memory distance and load in balance.

关键词： System-on-chip Educational institutions Load management Runtime Routing conferences Load modeling

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What cloud computing can teach us about embedded many-core programming?

What cloud computing can teach us about embedded many-core p...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： András Vajda Cloud Management Driver at Ericsson Finland

While seemingly worlds apart, cloud computing is confronted with many of the similar issues than embedded systems: power consumption, energy efficiency, optimal usage of resources such as processing cores and memory etc. This talk will explore how solutions and programming paradigms emerging in the cloud computing space can be used in the embedded space - and vice versa.

关键词： Cloud computing Programming Business computer architecture Abstracts embedded systems Power demand

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RAPIDO 2013 - Proc. of the 2013 Workshop on Rapid simulation and Performance Evaluation: Methods and Tools, in Conj. with the 8th Intl. Conf. on High-Performance and embedded architectures and Compilers, HiPEAC 2013

RAPIDO 2013 - Proc. of the 2013 Workshop on Rapid Simulation...

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2013 4th Workshop on Rapid simulation and Performance Evaluation: Methods and Tools, RAPIDO 2013 - In Conjunction with the 8th Intl. conference on High-Performance and embedded architectures and Compilers, HiPEAC 2013

ISBN: (纸本)9781450315395

The proceedings contain 6 papers. The topics discussed include: Simsys: a performance simulation framework;network-on-chip traffic modeling for data flow applications;exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systems;prototyping hardware support for irregular applications;TLM modelling of 3D stacked wide I/O DRAM subsystems;and using the CASM language for simulator synthesis and model verification.

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Special session on “Fault-tolerant techniques for computer systems, architectures and processors”

Special session on “Fault-tolerant techniques for computer ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ioannis Sourdis Chalmers University of Technology Sweden

ISBN: (纸本)9781479901043

As semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking device features. As a consequence, reliability is an increasing concern not only for safety-critical systems, but also for many other application domains in embedded systems. However, traditional solutions for fault tolerance, e.g. provided through various redundancy schemes, have disproportionally increasing power and performance costs. This, in turn, limits substantially systems' efficiency, especially due to the fact that performance scaling and power are becoming significant design challenges, too. In the face of such changes in the technological landscape, this special session offers original contributions for fault-tolerant computer systems, architectures and processors, which address the above challenges.

关键词： Special Session GPU GRAPPER PICK UP Graphics Processing Unit PROCESSOR hardware resource Fault tolerance redundancy permanent fault ARCHITECTURE computer systems faults programming environments semiconductor technology

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2013 Proceedings of the international conference on embedded software, EMSOFT 2013

2013 Proceedings of the international conference on embedded...

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13th international conference on embedded Software, EMSOFT 2013

ISBN: (纸本)9781479914432

The proceedings contain 31 papers. The topics discussed include: an efficient code update solution for wireless sensor network reprogramming;determinate composition of FMUs for co-simulation;BPDF: a statically analyzable dataflow model with integer and Boolean parameters;middleware design for physically-asynchronous logically-synchronous (pals) systems;diversifying wear index for MLC NAND flash memory to extend the lifetime of SSDS;a synchronous embedding of Antescofo, a domain-specific language for interactive mixed music;a characterization of integrated multi-view modeling in the context of embedded and cyber-physical systems;verifying Simulink diagrams via a hybrid Hoare logic prover;bit-precise formal verification of discrete-time MATLAB/Simulink models using SMT solving;safety verification for linear systems;diversely enumerating system-level architectures;on composing and proving the correctness of reactive behavior;and time-aware relational abstractions for hybrid systems.

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A Process-based Reconfigurable SystemC Module for simulation speedup

A Process-based Reconfigurable SystemC Module for simulation...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Efstathios Sotiriou-Xanthopoulos Kostas Siozios George Economakos Dimitrios Soudris School of Electrical and Computer Engineering National Technical University of Athens Athens Greece

ISBN: (纸本)9781479901043

As Multi-Processor systems-on-Chip (MPSoC) architectures become more and more complex, Design Space Exploration (DSE) becomes the only viable solution for finding the pareto-optimal designs. To evaluate each solution with real dataset, DSE has to simulate the design under test, which is modeled as a Virtual Platform usually written in SystemC. However, the simulation is a very slow task which includes non-productive time periods like system initialization, while the platform re-compilation also imposes a significant overhead. In this paper, a Process-based Reconfigurable Module is used in order to bypass the non-productive simulation parts, thus accelerating the simulation. The effectiveness of the proposed methodology is proved with a series of computationally intensive multimedia applications, where the simulation time improvements reach 34% on average.

关键词： Synchronization Delays Ports (computers) Runtime Servers Dynamic scheduling

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Dynamic task mapping onto multi-core architectures through stream rewriting

Dynamic task mapping onto multi-core architectures through s...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Lars Middendorf Christian Zebelein Christian Haubelt Institute of Applied Microelectronics and Computer Engineering University of Rostock Germany

ISBN: (纸本)9781479901043

Task graphs provide an efficient model of computation for specification, analysis, and implementation of concurrent applications. In this paper, we present a novel approach for mapping the class of series-parallel task graphs onto multi-core architectures based on pattern matching. Both the topology of the graph and the state of the tasks are encoded as a stream of tokens, which is iteratively rewritten at multiple positions in parallel. Hence, our technique is most useful for compute-intensive applications that must adapt to frequently varying and unpredictable workload at runtime. Several complex examples have been evaluated on a multi-core architecture and the experimental results show the effectiveness of our approach.

关键词： Multicore processing Computational modeling Runtime Program processors Synchronization Pattern matching

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High Speed Cycle Approximate simulation for Cache-Incoherent MPSoCs

High Speed Cycle Approximate Simulation for Cache-Incoherent...

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international conference on embedded computer systems: architectures, modeling and simulation

作者： Christopher Thompson Miles Gould Nigel Topham Institute for Computing Systems Architecture University of Edinburgh United Kingdom

ISBN: (纸本)9781479901043

We present a new high speed cycle-approximate simulator, addressing an important, neglected category of multi-core systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. We present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average we simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%.

关键词： MIPS FPGA MPSoCs

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Special session on “Exposed data path architectures: Recent advances and applications”

Special session on “Exposed data path architectures: Recent...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Jani Boutellier Pekka Jääskeläinen University of Oulu Finland Tampere University of Technology Finland

The concept of “exposed datapath” is used in conjunction with processor architectures where the programmer can control more fine grained details of the datapath than in “traditional” processor architectures. For example, Transport Triggered architectures (TTA) expose the data transports between the register files and function units for the direct control of the programmer. Some architectures, while otherwise having a general purpose register based instruction-set, allow the programmer to explicitly route previously computed results from a function unit to the next one to implement register bypassing in software. The additional datapath control extends the instruction scheduling freedom, simplifies the control hardware logic, eases the customization of the datapath interconnection network, and increases the instruction-level parallelism scalability, with the obvious drawbacks of wider instruction words and added compilation complexity.

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