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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Medical Image Scalar for Portable Medical Devices

Medical Image Scalar for Portable Medical Devices

引用

AIML-applications for Engineering & Technology (ICAET), international conference on

作者： Mrinalini Joshi Pangaonakar P.P. Shingare Dept of E&TC Engineerig College of engineering Pune Pune India

ISBN: (数字)9798350355611

ISBN: (纸本)9798350355628

The field of Image processing is playing a vital role in making technological changes those results in real time applications. Image scaling is one of such fundamental method that helps to resolve storage issue and also helps for fast image data transmission. The technique is beneficial in case of real time portable devices and similar applications as usually the scaling required at end user device. This paper proposes medical image scalar for portable medical devices implemented using FPGA which involves creating a compact, efficient, and reliable system capable of adjusting the size and resolution of medical images for display on different devices This medical image scalar can be used for applications such as portable medical devices for remote disease diagnosis, image assisted surgery and other telemedicine applications where image quality, processing power and energy efficiency are of critical concerns. The proposed medical image scalar involves polynomial based enhanced bilinear interpolation technique for image scaling that preserves the image quality and also make VLSI implementation easier.

关键词： Image quality Medical devices Image resolution Telemedicine Surgery Very large scale integration Real-time systems Energy efficiency Medical diagnostic imaging field programmable gate arrays

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Design, Analysis and Verification of AMBA AXI4.0

Design, Analysis and Verification of AMBA AXI4.0

引用

Visual Analytics and Data Visualization (ICVADV), international conference on

作者： Aashima Lalit Mohan Saini School of VLSI and Embedded System Design National Institute of Technology Kurukshetra Haryana India Department of Electrical Engineering National Institute of Technology Kurukshetra Haryana India

ISBN: (数字)9798331521394

ISBN: (纸本)9798331521400

AMBA AXI was developed by ARM in 2003 upgrading it to AMBA AXI 4.0 in 2014. AMBA AXI4.0 is a fast, efficient, high frequency, high performance, high bandwidth SOC (system-on-chip) protocol that is used for communication between CPU (central processing unit) and FPGA (field programmable gate arrays). It has five communication channels for reading and writing between master and slave. It supports burst transactions and has handshake mechanism, which makes it suitable for high data transfers rate and for pipeline processing of instructions. It finds applications in various ARM (advanced RISC (reduced instruction set computer) machine) based FPGAs like Zynq-7000, Zynq Ultrascale+, Spartan 7, Arria 10 etc. This work implements the AXI4.0 protocol for communication between master and slave for 32 bits of data transfer and verification of using protocol checker.

关键词： Reduced instruction set computing Visual analytics Communication channels Writing Data transfer Main-secondary Central Processing Unit System-on-chip field programmable gate arrays Pipeline processing

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Demo: An RFSoC-Based Testbed for Over-the-Air Wireless Transceiver at Millimeter Wave Frequency

Demo: An RFSoC-Based Testbed for Over-the-Air Wireless Trans...

引用

international Communication Systems and Networks and Workshops, COMSNETS

作者： Jeet Tekchandani Jai Mangal Sumit J. Darak Shobha Sundar Ram Electronics & Communication Department Indraprastha Institute of Information Technology Delhi India

ISBN: (数字)9798331531195

ISBN: (纸本)9798331531201

The millimeter wave (mmW) frequency spectrum has been explored recently for large bandwidth communication. At these frequencies, narrow directional beams are required for communication since the signal attenuation is high due to atmospheric absorption. This work presents an AMD RFSoC and Sivers Semiconductors analog front-end based hardware testbed capable of directional communication via analog beamforming at mmW. The proposed testbed comprises orthogonal frequency division multiplexing (OFDM) based baseband physical layer and digital front-end on an ARM processor and field programmable gate array (FPGA), respectively, integrated with high-speed data converters of the RFSoC. The RFSoC output at sub-6GHz is integrated with a mmW multi-antenna analog-front end for over-the-air communication at 29.8 GHz. We demonstrate end-to-end communication over the air and present bit error rate (BER) analysis in the presence of radio frequency impairments and beam misalignments in real radio channels.

关键词： OFDM Wireless networks Bit error rate logic gates Physical layer Hardware Transceivers Frequency division multiplexing Millimeter wave communication field programmable gate arrays

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Low-Power and Superior Performance Design of Ternary logic Cells Using CNFET and MOSFET Devices for VLSI applications

Low-Power and Superior Performance Design of Ternary Logic C...

引用

international conference on VLSI Design

作者： Siva Chinmai Varma Bhupathiraju Sridhara Sai Krishna Yashwanth Komuravelly Ramakant Yadav Dept. of Electrical and Computer Engineering Mahindra University Hyderabad Telangana India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This work explores the implementation of ternary logic using novel devices, particularly Carbon Nanotube field Effect Transistors (CNFETs). CNFETs leverage single-walled carbon nanotubes as conducting channels, and by adjusting the diameter of the carbon nanotubes, we can control the device's threshold voltage. This characteristic makes CNFETs well-suited for ternary logic, as we can easily create Low Voltage Threshold (LVT) and High Voltage Threshold (HVT) devices required for implementing ternary logic. Optimized MOSFET and CNFET, N, and P-channel devices are benchmarked and compared at 45 nm technology node. Furthermore, we present the design and functionality of ternary inverters using both MOSFETs and CNFETs, including Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), and Standard Ternary Inverter (STI). The performance of all the logic cells mentioned in the paper was benchmarked and it is observed that CNFET ternary cells have lower PDP compared to MOSFET ternary cells. A decrease of 23.78% and 20.78% in PDP is observed for NTI and PTI logic cells, respectively, and a decrease of 29.65% and 29.35% is observed for STI 1 and STI 2 logic cells, respectively.

关键词： Semiconductor device modeling Performance evaluation MOSFET Very large scale integration Carbon nanotubes Multivalued logic CMOS technology Inverters CNTFETs Delays

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Advancements in Real-Time Image Processing Using Kintex and Virtex FPGAs: Enhancing Speed, Efficiency, and Versatility

Advancements in Real-Time Image Processing Using Kintex and ...

引用

Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), IEEE conference on

作者： Shishir Shrivastava Bura Vijay Kumar Rupesh Gupta Vibhor Sharma Institute of Engineering and Technology Chitkara University School of Computer Science and Artificial Intelligence SR University Warangal Telangana India University of New Haven

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

Image processing is a critical component in various applications, ranging from medical imaging to autonomous systems. This research explores the utilization of high-performance field programmable Gate Arrays (FPGAs) such as Kintex and Virtex to enhance image processing capabilities. By leveraging the parallel processing power and reconfigurability of these FPGAs, the study achieves significant improvements in processing speed and efficiency, enabling real-time image analysis and decision-making. This advancement supports the United Nations’ Sustainable Development by enhancing smart city technologies. The implementation of Kintex and Virtex in image processing not only drives innovation but also contributes to building resilient and sustainable infrastructures, thereby promoting well-being and sustainable urban development.

关键词： Technological innovation Smart cities Autonomous systems Image processing Scalability Decision making Real-time systems Distance measurement Sustainable development field programmable gate arrays

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Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI

Radiation Degradation Evaluation of the Dynamic Configuratio...

引用

IEEE international conference on Consumer Electronics (ICCE)

作者： Seiji Ohashi Minoru Watanabe Nobuya Watanabe Information Technology Track Information Technology Electrical Engineering and Mathematical and Data Sciences Program Faculty of Engineering Okayama University Kita-ku Okayama Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

The Fukushima Daiichi Nuclear Power Plant was melted down by the earthquake and tsunami in 2011. The decommissioning tasks must be executed under a high radiation intensity. For the tasks, we have been developing a radiation-hardened optically reconfigurable gate array with 1 Grad total-ionizing-dose tolerance. In this device, dynamic optical parallel configuration architecture was introduced to increase the radiation tolerance. However, the radiation degradation evaluation has never been done up to now. This paper presents the first evaluation results of the dynamic optical parallel configuration circuit on an optically reconfigurable gate array VLSI.

关键词： Integrated optics Degradation Earthquakes Very large scale integration logic gates Tsunami Power generation field programmable gate arrays Consumer electronics Optical arrays

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Evaluating HLS4ML For Converting a CNN Model Into High Level Synthesis

Evaluating HLS4ML For Converting a CNN Model Into High Level...

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Advanced Research in Computing (ICARC), international conference on

作者： Noura Jariri Mohammed Chaman Rania Majdoubi Abdelkader Hadjoudja Electronic Systems Information Processing Mechanics and Energy Laboratory Faculty of Science Ibn Tofail University Kenitra Morocco

ISBN: (数字)9798331530983

ISBN: (纸本)9798331530990

Deep learning models, although high-performing, often require hardware acceleration to be effectively deployed on field programmable Gate Arrays (FPGAs). This paper investigates the use of the hls4ml framework to convert a Convolutional Neural Network (CNN) model into High Level Synthesis (HLS). hls4ml is a Python tool that translates neural networks into FPGA-compatible firmware for high-performance inference with reduced latency and power usage. It employs High-Level Synthesis (HLS) techniques to translate high-level programming languages like C++ or Python into hardware description languages, such as VHDL or Verilog. We evaluate the model’s performance in terms of accuracy and demonstrate the effectiveness of converting a deep learning model, specifically a CNN, for hardware implementation. The results highlight the potential of hls4ml facilitating embedded artificial intelligence applications, offering an efficient and scalable solution for deploying deep learning models on resource-constrained platforms.

关键词： Deep learning Accuracy Embedded systems VHDL Predictive models Software High level synthesis Convolutional neural networks field programmable gate arrays Python

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2nd international Workshop on field-programmable logic and applications, FPL 1992

引用

2nd international Workshop on field-programmable logic and applications, FPL 1992

ISBN: (纸本)9783540570912

The proceedings contain 23 papers. The special focus in this conference is on field-programmable logic and applications. The topics include: Overview of complex array-based PLDS;technologies and utilization of field programmable gate arrays;some considerations on field programmable gate arrays and their impact on system design;sram-based FPGAs ease system verification;an FPGA for synchronous and asynchronous circuits;a new architecture for high-performance FPGAs;patching method for lookup-table type FPGA's;automatic one-hot re-encoding for FPGAs;minimization of permuted reed-muller trees for cellular logic programmable gate arrays;self-organizing kohonen maps for FPGA placement;high level synthesis in an FPGA-based computer aided prototyping environment;new application of FPGAs to programmable digital communication circuits;FPGA based logic synthesis of squarers using VHDL;optimized fuzzy controller architecture for field programmable gate arrays;a real-time kernel — rapid prototyping with VHDL and FPGAs;JAPROC — a 8 bit micro controller design and its test environment;a workstation of a different colour;a highly parallel FPGA-based machine and its formal verification;FPGA based self-test with deterministic test patterns;using FPGAs to prototype a self-timed computer;using FPGAs to implement a reconfigurable highly parallel computer and novel high performance machine paradigms and fast-turnaround asic design methods.

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field-programmable logic: Architectures, synthesis and applications: 4th international workshop on field-programmable logic and applications, FPL’94 Prague, Czech Republic, september 7–9, 1994 proceedings 4th

Field-programmable logic: Architectures, synthesis and appli...

引用

4th international Workshop on field-programmable logic and applications, FPL 1994

作者： Hartenstein, Reiner W. Servít, Michal Z. Fachbereich Informatik Universität Kaiserslautern Postfach 3049 KaiserslauternD-67653 Germany Department of Computers Czech Technical University Karlovo mimfistf 13 Prague 212135 Czech Republic

ISBN: (纸本)9783540584193

This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit. © Springer-Verlag Berlin Heidelberg 1994.

关键词： field programmable gate arrays (FPGA)

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Design and Performance Research of Multi Channel Acquisition Module

Design and Performance Research of Multi Channel Acquisition...

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Power Electronics, Computer applications (ICPECA), IEEE international conference on

作者： Xiqiang Jin Wei Wang Nantian Ruan Aijun Zhao Yalong He Hangzhou Applied Acoustics Research Institute Hangzhou China

ISBN: (数字)9798331533694

ISBN: (纸本)9798331533700

With the rapid development of signal acquisition technology, the requirements for signal acquisition resolution, sampling rate, and data processing speed are increasing in applications such as radar signals, communication, and intelligent transportation. Therefore, it is urgent to solve how to improve the sampling rate and resolution to meet the current demand for high precision and high sampling rate. This article uses multiple dual channel A/D sampling chips (with a sampling rate of 100MSPS and a resolution of 16 bits), implements synchronous sampling and data transmission based on FPGA, and completes functional and performance verification. The data collected by FPGA can be sent to the processor or upper computer for further data processing and storage through standard network protocols and SRIO protocols. Through practical application in signal processing systems, it has been verified that the multi-channel acquisition module has advantages such as universality and flexible scalability, and has certain application value in engineering applications.

关键词： Protocols Scalability Transportation Signal processing algorithms Data processing Radar signal processing Reliability Signal resolution field programmable gate arrays Standards

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