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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是111-120 订阅

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Empowering Smart Living: FPGA-Enabled Home Automation for Enhanced Safety, Security, and Efficiency

Empowering Smart Living: FPGA-Enabled Home Automation for En...

引用

Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), IEEE conference on

作者： Narendra Singh Beniwal Shruti Kalra Ruby Beniwal Department of Electronics and Communication BIET Jhansi UP India Department of Electronics and Communication Jaypee Institute Of Information Technology Noida India

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

This paper presents an FPGA-based home automation system implemented on a Xilinx Zynq-7000 SoC. Using Verilog HDL, FSM logic handles sensor signals (fire sensor: 5V, digital; buzzer: 5-12V). Cadence tools generated verified RTL schematics and waveforms. Key features include automated lighting, temperature regulation, and fire/intruder alerts, with a detection threshold of 3 seconds. The modular system ensures scalability, supporting seamless integration of additional devices for enhanced functionality and security.

关键词： Automation Accuracy Scalability Feature extraction Motion detection Security Time factors Hardware design languages Usability field programmable gate arrays

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Detection of Beer Bottle Caps with Defects Based on Improved ShuffleNet V2

Detection of Beer Bottle Caps with Defects Based on Improved...

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Electrical Automation and Artificial Intelligence (ICEAAI), international conference on

作者： Jie Luo Xingcheng Liu Renwei Ou Yitong Liu Yang Yi School of Electronics and Information Technology Sun Yat-sen University Guangzhou China School of Information Intelligent Engineering Guangzhou Xinhua University Guangzhou China Department of Electrical & Computer Engineering University of Waterloo Waterloo Canada Department of Computer Science Sun Yat-sen University Guangzhou China

ISBN: (数字)9798331506797

ISBN: (纸本)9798331506803

Beer bottle caps are produced in large quantities. In addition, beer bottle caps with defects not only affect the customer's experience, but also may not protect the beer effectively. Therefore, it is important to detect defects in beer bottle caps quickly, efficiently and accurately. Deploying convolutional neural network (CNN) on field programmable gate array (FPGA) can achieve the above objectives. However, CNN generally has a large number of parameters and high complexity, in addition, CNN operates differently among different hardware devices. In order to solve the problems, this paper improves the ShuffleN et V2 so that the model is suitable to be deployed on FPGA, and runs fast on FPGA. The improved methods are shown below: firstly, we reduce the number of output channels in the Conv5 module. After that, we replace the $1\times 1$ ordinary convolutions of the right branch in the ShuffleNet V2 Unit1 and Unit2 with the $1\times 1$ group convolutions, and add the channel shuffle after the first group convolution. Finally, we replace the convolution operations of the left branch in the ShuffleN et V2 U nit2 with the max pooling. Experiments show that our proposed model not only reduces the number of parameters and the complexity of the model, but also improves the accuracy and the f1-score of the model.

关键词： Accuracy Automation logic gates Hardware Complexity theory Convolutional neural networks Artificial intelligence field programmable gate arrays

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FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs

FPUGen: A FrameWork to Generate Custom Floating Point FMA Ac...

引用

international conference on VLSI Design

作者： Himanshu Rai Aishwarya Sridhar Wolfgang Ecker Nanditha Rao International Institute of Information Technology Bangalore India Infineon Technologies Semiconductor India Pvt. Ltd. Infineon Technologies AG Neubiberg Bavaria Germany

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Floating-point representations enable finer granularity of computations, improving the overall accuracy of ML models. Approximate computing techniques using variable bit-width can be employed to reduce the computational complexity of training algorithms while maintaining an acceptable level of accuracy. In this work, we propose FPUGen: a framework to generate custom floating-point (FP) fused multiply-add (FMA) accelerators. The accelerators have several architectural highlights such as: (a) Reconfigurable FP-FMA units for any mantissa and exponent size, (b) Dynamic precision FMA (DFMA) support for one SP-32, two TF-32, two HP-16, or three BF-16 operations in parallel, (c) Rounding logic for dynamic precision and (d) pipelined/non-pipelined FP-FMA architecture support. We note that choosing BF-16 over DP-64 and SP-32 saves energy by 5.73x and 2.56x respectively on an FPGA. Our proposed DFMA-V2 architecture is 1.49x more resource efficient, has 3.85x better throughput, and is 1.71x more energy efficient compared to the baseline design (DFMA-V1) due to the pipelined and resource-sharing architecture. It achieves a maximum throughput of 56.10 GFLOP/s on the ZCU104 FPGA, which is 5.8x higher than the baseline design.

关键词： Training Accuracy Heuristic algorithms Computer architecture Switches Very large scale integration Throughput Energy efficiency logic field programmable gate arrays

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Design and Optimization of Efficient CNN Hardware of Digital Number Recognition for Low-Power

Design and Optimization of Efficient CNN Hardware of Digital...

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international conference on Signal Processing and Communication (ICSC)

作者： Prakash Kumar Anshuj Jain Laxmi Singh Sr. Manager Physical Design Tech Mahindra Bangalore India Electronics and communication RNTU Bhopal India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

This paper offers a unique convolutional neural network (CNN) architecture optimized for digital number recognition, emphasising low powerconsumption. The project attempts to create an efficientCNN-based system capable of detecting digital numbers in power-constrained conditions. We use a cutting-edge YOLO-NAS model and FPGA (field programmable Gate Array) technology to improve processing efficiency and minimize energy consumption. The technique consists of many critical components. First, we train the YOLO-NAS model using a large dataset from Roboflow, which includes extensive annotations for digital number recognition. The model is then modified for FPGA implementation, necessitating changes to accommodate FPGA-specific limitations and assure compatibility. To enhance the model performance, we use quantization techniques and pruning strategies, particularly the L1 norm-based pruning strategy, which reduces model size and Computing demand while maintaining accuracy. Thefindings reveal that our FPGA-based YOLO-NAS modeloutperforms traditional GPU-based systems in terms of power efficiency while not influencingrecognition performance. The model performs well in real-time digital number recognition tests, showing its usefulness in low-power applications. This study overcomes the issues of power consumption and processing efficiency, providing a scalable approach appropriate for edge computing applications. By combining YOLO-NAS with FPGA, the research opens the path for more sustainable and efficient digital recognition systems.

关键词： Training Power demand Accuracy Computational modeling Graphics processing units Computer architecture Hardware Real-time systems Convolutional neural networks field programmable gate arrays

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4th international Workshop on field-programmable logic and applications, FPL 1994

4th International Workshop on Field-Programmable Logic and A...

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4th international Workshop on field-programmable logic and applications, FPL 1994

ISBN: (纸本)9783540584193

The proceedings contain 63 papers. The special focus in this conference is on field-programmable logic and applications. The topics include: A test methodology applied to cellular logic programmable gate arrays;influence of logic block layout architecture on FPGA performance;a global routing heuristic for FPGAs based on mean field annealing;power dissipation driven FPGA place and route under delay constraints;FPGA technology mapping for power minimization;specification and synthesis of complex arithmetic operators for FPGAs;a speed-up technique for synchronous circuits realized as LUT-based FPGAs;an efficient technique for mapping RTL structures onto FPGAs;a testbench design method suitable for FPGA -based prototyping of reactive systems;using consensusless covers for fast operating on Boolean functions;formal verification of timing rules in design specifications;a high-speed rotation processor;a reprogrammable processor for fractal image compression;implementing GCD systolic arrays on FPGA;formal cad techniques for safety-critical FPGA design and deployment in embedded subsystems;FPGA based reconfigurable architecture for a compact vision system;a new FPGA architecture for word-oriented datapaths;image processing on a custom computing platform;a superscalar and reconfigurable processor;a fast FPGA implementation of a general purpose neuron;data-procedural languages for FPL-based machines;implementing on line arithmetic on PAM;constraint-based hierarchical placement of parallel programs;simulating static and dynamic faults in BIST structures with a FPGA based emulator;meaningful benchmarks for logic optimization of table-lookup FPGAs and educational use of field programmable gate arrays.

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Real-Time Flexible Accelerator for Fisheye Image Correction Based on Zynq SoC

Real-Time Flexible Accelerator for Fisheye Image Correction ...

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Mechatronics and Robotics Engineering (ICMRE), international conference on

作者： HoBin Oh Gyu Hyeon Hwang Jae Wook Jeon Department of Electrical and Computer Engineering Sungkyunkwan University Suwon Korea

ISBN: (数字)9798331509293

ISBN: (纸本)9798331509309

Fisheye cameras' broad field of view makes them ideal for a variety of applications, such as robotic navigation, drone vision, and car surround-view systems. Fisheye eyeglasses' intrinsic nonlinear distortion, however, makes it difficult to accurately interpret images and analyze them later. This research proposes a Zynq System on Chip (SoC)-based accelerator to dynamically restore fisheye lens image distortion in real time. The proposed system improves the limitations of conventional field programmable gate array (FPGA) designs that require fixed parameters and leverages the Python Productivity for Zynq (PYNQ) framework to enable dynamic parameter modification without reprogramming. Experimental results show that the proposed system processes images with a resolution of 960x640 at a speed of 135.7 frames per second (fps), achieving more than 20 times faster performance compared to software-based solutions. Additionally, it can maintain real-time performance even at Full HD resolution. We also evaluated the accuracy by comparing the fisheye distortion correction of four interpolation techniques provided by OpenCV with the quality indicators Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM). It is also flexible enough to allow the system to dynamically adapt to environmental changes and process images efficiently. This research provides a highly flexible, real-time fisheye distortion correction system for various industries such as robotics, automotive, and drones.

关键词： Image resolution PSNR Navigation Nonlinear distortion Real-time systems System-on-chip Automobiles Vehicle dynamics field programmable gate arrays Drones

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Design and Research of AI Accelerators for Onboard Computing Platforms Targeting YOLOs Network

Design and Research of AI Accelerators for Onboard Computing...

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international conference on Computer Research and Development (ICCRD)

作者： Yunlong Wang Hui Zhou Xia Liu Bing Li Yifan Ge Beijing Aerospace Automatic Control Institute Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (数字)9798331531881

ISBN: (纸本)9798331531898

Convolutional Neural Networks (CNNs) play a crucial role in computer vision, with wide applications in image recognition, object tracking, and trajectory optimization. Due to constraints in computation, power consumption, and size in aerospace vehicles, deploying CNN algorithms on target platforms presents a significant challenge in aerospace applications. This paper proposes an accelerator design for the YOLOv3-tiny network tailored to aerospace applications. By employing techniques such as loop partitioning, loop unrolling, and weight sharing, the proposed accelerator enhances computational performance and data reuse efficiency. Additionally, by integrating convolution, activation, and pooling operations into a unified module, this approach reduces the need for intermediate buffers, saving memory and improving acceleration performance. Compared to accelerators that require buffering of convolution results, the proposed design demonstrates superior performance. The accelerator is implemented on the ZYNQ7020 FPGA platform, achieving a peak computational performance of 114.53 GOPS.

关键词： Convolution Computational efficiency Partitioning algorithms Timing Convolutional neural networks field programmable gate arrays Trajectory optimization Research and development Pipeline processing Radio spectrum management

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Emerging field of NoC-Based Convolution Architecture with Systolic Arrays

Emerging Field of NoC-Based Convolution Architecture with Sy...

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international conference on Communication Systems and Network Technologies (CSNT)

作者： Chandana Gadikota Vijaya Lakshmi P Dept of ECE VFSTR Guntur India

ISBN: (数字)9798331531935

ISBN: (纸本)9798331531942

Neural networks are widely used in image detection and identification applications because of their efficacy in handling complex problems. However, they require substantial memory bandwidth and CPU operations, limiting the performance of conventional CPUs. To address this challenge, researchers have developed an FPGA hardware accelerator for Convolution Neural Networks (CNNs). To enhance acceleration performance in CNNs, researchers have identified three key techniques: parallelization, memory optimization, and specialized data flow. A new network on-Chip paradigm was created by the researchers to reduce the off-chip memory Optimization according to researchers, a Network-on-Chip (NoC) architecture and Systolic Arrays (SA) have been created to enhance runtime, computational efficiency, and throughput while reducing off-chip memory traffic. In this paper recent trends in the NoC-Based CNN architecture have been represented.

关键词： Runtime Convolution Memory management Neural networks Network-on-chip Market research Systolic arrays Convolutional neural networks field programmable gate arrays Optimization

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Real-Time Aerial Image Edge Detection with MicroWatt Power ISA on FPGA

Real-Time Aerial Image Edge Detection with MicroWatt Power I...

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Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), international conference

作者： Prashant V Joshi Sudharshan K M Majunath G Asuti Poornashree S J Sunitha K Research School of ECE REVA University Bengaluru India Department of ECE BNMIT Bengaluru India

ISBN: (数字)9798331515911

ISBN: (纸本)9798331515928

This research investigates the implementation of real-time aerial image edge detection using the Canny edge detection algorithm with the MicroWatt Power Instruction Set Architecture (ISA)-Open Core Processor on field programmable Gate Arrays (FPGAs). Canny edge detection is particularly advantageous for aerial image processing due to its ability to produce precise and well-defined edges, making it ideal for applications in surveillance, agriculture, and environmental monitoring where detail preservation is critical. The proposed system utilizes the MicroWatt Power ISA-Open core processor to optimize resource utilization, achieving high throughput and low latency while maintaining energy efficiency. The work uses the Xilinx Vivado EDA tool to calculate the power dissipation of the FPGA implementation, demonstrating significant reductions in power consumption compared to traditional processing methods. The experimental results showcase the effectiveness of the Canny edge detector in producing accurate edge maps while minimizing resource usage, thus enabling real-time processing capabilities. This work contributes to the advancement of low-power embedded systems for aerial imaging, highlighting the potential of FPGAs combined with the MicroWatt Power ISA for efficient and effective image analysis.

关键词： Image edge detection Instruction sets Surveillance Imaging Throughput Real-time systems Power dissipation Resource management Environmental monitoring field programmable gate arrays

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Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA

Demonstration of a Clock Distribution Method using Switching...

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IEEE international conference on Consumer Electronics (ICCE)

作者： Ayumu Ogura Minoru Watanabe Nobuya Watanabe Information Technology Track Information Technology Electrical Engineering and Mathematical and Data Sciences Program Faculty of Engineering Okayama University Okayama Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Very large-scale Integrations (VLSIs) are vulnerable to radiation, and VLSIs used in high radiation environments such as space environment and nuclear power plants have a short lifetime. Therefore, we are developing radiation-hardened optically reconfigurable gate arrays. Conventional optically reconfigurable gate array VLSIs have a weak point in clock distribution. This problem can be solved by a new clock distribution exploiting reconfigurable switching matrices. However, in this case, the clock skew increases. Therefore, to solve this problem, this paper proposes a new clock distribution method using a two-phase clock signal and switching matrices on an optically reconfigurable gate array VLSI. The proposed clock distribution method has been demonstrated on a Cyclone V FPGA by using a 4-bit counter circuit. This paper presents the demonstration results.

关键词： Integrated optics Optical switches Radiation detectors logic gates Very large scale integration Adaptive optics field programmable gate arrays Power generation Clocks Optical arrays

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