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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是121-130 订阅

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Recent Advances in Battery Management System for Li-Ion Type EVs with Predictive Control and FPGA

Recent Advances in Battery Management System for Li-Ion Type...

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Smart and Sustainable Developments in Electrical Engineering (SSDEE), IEEE international conference on

作者： Sachidananda Sen Maneesh Kumar Basetti Vedik Chandan Kumar Shiva Dept. of EEE SR University Warangal Telangana India Dept. of HRE IIT Roorkee Uttarakhand India

ISBN: (数字)9798331542108

ISBN: (纸本)9798331542115

The increasing acceptance of electric vehicles (EVs) shows the significance of efficient and reliable battery management systems (BMS) for ensuring safety, optimizing the performance, and extend battery life. Various BMS algorithms exists in literature. Model Predictive Control (MPC) is a powerful tool due to its ability to handle multi-variable control processes and incorporate system constraints has also been considered for BMS design. Further, with the high computational demands of MPC, field programmable Gate Arrays (FPGAs) are also being integrated to enhance real-time processing capabilities, making BMS solutions for lithium-ion (Li-ion) batteries more effective. In recent times, the Li-ion batteries are considered to be the most suitable for EVs. This fiat has resulted from many years of research and development that improved Li-ion's performance in comparison to Lead-acid, Nickel, Sodium based batteries. Despite these advantages, still there exists some key challenges in terms of safety, cost-effectiveness, longevity, recycling, and degradation. To adhere these concerns, BMS is used in the EVs for proper use of the Li-ion batteries that reduces number of charging and discharging cycles, estimates various health parameters of the battery such as state-of-charge (SoC), state-of-health (SoH), regulates the cell temperature, and computes the degradation. This paper reviews recent advances in BMS using MPC and FPGA, assessing developments in modeling, control strategies, hardware implementation, and testing frameworks. Innovations that address the challenges of state estimation, fault detection, and system efficiency are emphasized for current research and future directions.

关键词： Lithium-ion batteries Degradation Battery management systems logic gates Prediction algorithms Real-time systems Hardware Safety field programmable gate arrays Predictive control

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Sensitivity Analysis of Dielectric Modulated Dual Gate Gallium Nitride Junctionless Accumulation Mode Nanowire FET Based Biosensor

Sensitivity Analysis of Dielectric Modulated Dual Gate Galli...

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international conference on Signal Processing and Communication (ICSC)

作者： Anupama Sonam Rewari Neeta Pandey Department of Electrical Engineering Delhi Technological University Delhi India Department of Electronics and Communication Engineering Delhi Technological University Delhi India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

This study investigates the Dielectric Modulated Dual Metal Gate Gallium Nitride Junctionless Accumulation Mode Nanowire FET (DM-DG-GaN-JAM-NWFET) as a potential biosensor for applications in the biomedical field. To assess its sensing capabilities, neutral and charged biomolecules are analyzed, focusing on the effects of different dielectric constants and charge densities on the device's electrostatic properties. Key parameters, including threshold voltage (V TH ) and on-current (Ion) are examined to evaluate the sensitivity of device. Additionally, the performance of the Dual Metal Gate Gallium Nitride Junctionless Accumulation Mode (DG-GaN-JAM) Nanowire FET is compared with that of the Single Metal Gate Gallium Nitride Junctionless Accumulation Mode (SG-GaN-JAM) Nanowire FET. The results highlight that the DM-DG-GaN-JAM-NWFET biosensor is highly effective for biosensing applications.

关键词： Sensitivity analysis field effect transistors Metals Molecular biophysics logic gates Signal processing Threshold voltage Sensors Biosensors Gallium nitride

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Evaluation of Multi-Bit Input logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration

Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed F...

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international Electrical Engineering Congress (iEECON)

作者： Tomoaki Sato Anyu Murakami Sorawat Chivapreecha Phichet Moungnoul Dept. of Management Information Hokusei Gakuen University Sapporo Japan School of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

ISBN: (数字)9798331543952

ISBN: (纸本)9798331543969

This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm 2 , outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.

关键词： Power demand Routing Rendering (computer graphics) Delays Table lookup logic field programmable gate arrays Optimization Pattern matching Faces

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FPGA-based Real-Time Spectral Peak Estimator for Radar Altimeter Signal Analysis

FPGA-based Real-Time Spectral Peak Estimator for Radar Altim...

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international conference on Communication Systems and Network Technologies (CSNT)

作者： Ritesh Kumar Sharma Jolly Dhar Umang Bhatia B Saravana Kumar Ch V N Rao D R Chowdhury Space Applications Centre Indian Space Research Organisation (ISRO) Ahmedabad India Department of Computer Science and Engineering Indian Institute of Technology (IIT) Kharagpur India

ISBN: (数字)9798331531935

ISBN: (纸本)9798331531942

This research work presents Real-Time Spectral Peak Estimator for radar altimeter signal analysis on an FPGA- based platform, focusing on accurate beat frequency estimation for precise above-ground level (AGL) altitude measurements. The proposed design is based on the first-order derivative difference estimator combined with zero crossover point detection to identify spectral maxima efficiently. This estimator is implemented using a fixed-point concurrent FPGA architecture to achieve high computational efficiency, low latency, and optimal hardware utilization, enabling real-time processing of radar return signals. This system has been verified and validated during various lab and field tests for the accurate beat frequency estimation under the dynamic signal conditions. The solution meets the stringent performance requirements of radar altimeter applications, making it suitable for aerospace, autonomous landing, and navigation systems where real-time accuracy is critical.

关键词： Accuracy Fast Fourier transforms Aerodynamics Real-time systems Frequency estimation Hardware Robustness Signal analysis Low latency communication field programmable gate arrays

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Random Number Generators and Sphere Sampling for High-Level Synthesis

Random Number Generators and Sphere Sampling for High-Level ...

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IEEE international conference on Consumer Electronics (ICCE)

作者： Syuji Onishi Yuuto Asaumi Tomonori Izumi Motoya Takenaka Dept. of Electronic and Computer Eng. Col. of Sci. & Eng. Dept. of Electronic Systems Grad. Schl. of Sci. & Eng. Inst. of Disaster Mitigation for Urban Cultural Heritage Ritsumeikan Univ. Shiga Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Randomized algorithms are often utilized for applications such as path planning in autonomous mobile systems. FPGAs are considered a solution candidate for the computation to cope with the heavy load caused by the huge number of iterations. This paper presents our designs of Random Number Generators (RNGs) for FPGAs, including Mersenne Twister, Combined Tausworthe, and Sphere Sampling. We utilize High-Level Synthesis (HLS) design tools for productivity and tune the code considering the resultant architecture for performance.

关键词： Productivity Codes Computer architecture Generators Path planning Design tools field programmable gate arrays Consumer electronics

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Design and Implementation of Single Master Single Slave Serial Peripheral Interface (SPI) on FPGA

Design and Implementation of Single Master Single Slave Seri...

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IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Shardul Penurkar Abhishek Kumar Saurabh Srivastava Sangeeta Nakhate Department of Electronics and Communication Engineering Maulana Azad National Institute of Technology Bhopal India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

This paper presents the design and analysis of a Single Master Single Slave Serial Peripheral Interface (SPI) system implemented on an FPGA. SPI is a communication protocol that enables data transfer between devices by designating master and slave roles. Despite its utility, existing peripheral communication protocols have limitations. While parallel communication requires extensive wiring and is prone to noise and crosstalk, serial communication can be slower, consume more power, and result in lower throughput. This study aims to develop an SPI module optimized for single-slave operation. Simulations conducted using AMD Vivado confirmed the module's functionality, and the design was successfully implemented on a Nexys 4 DDR FPGA board. In conclusion, the Single Master Single Slave SPI module was effectively designed and verified.

关键词： Wiring Noise logic gates Throughput Main-secondary Software Reliability Hardware design languages field programmable gate arrays Testing

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Compact and Efficient Neural Networks for Image Recognition Based on Learned 2D Separable Transform

Compact and Efficient Neural Networks for Image Recognition ...

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Digital Signal Processing and its applications (DSPA), international conference on

作者： Maxim Vashkevich Egor Krivalcevich Department of Computer Engineering Belarusian State University of Informatics and Radioelectronics Minsk Belarus

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

The paper presents a learned two-dimensional separable transform (LST) that can be considered as a new type of computational layer for constructing neural network (NN) architecture for image recognition tasks. The LST based on the idea of sharing the weights of one fullyconnected (FC) layer to process all rows of an image. After that, a second shared FC layer is used to process all columns of image representation obtained from the first layer. The use of LST layers in a NN architecture significantly reduces the number of model parameters compared to models that use stacked FC layers. We show that a NN-classifier based on a single LST layer followed by an FC layer achieves 98.02% accuracy on the MNIST dataset, while having only 9.5k parameters. We also implemented a LST-based classifier for handwritten digit recognition on the FPGA platform to demonstrate the efficiency of the suggested approach for designing a compact and high-performance implementation of NN models.

关键词： Accuracy Image recognition Quantization (signal) Two-dimensional displays Transforms Artificial neural networks Computer architecture Image representation field programmable gate arrays Image classification

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Performance Analysis of Quaternary to Binary Converter Implemented Using FinFET models

Performance Analysis of Quaternary to Binary Converter Imple...

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Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), IEEE conference on

作者： Mohit Kumar Goel Kulbhushan Sharma Sripelli Jagadish Amaar Haamid Shnaeen VLSI Centre of Excellence Chitkara University Institute of Engineering and Technology Chitkara University Punjab India School of Computer Science and Artificial Intelligence SR University Warangal Telangana India Department of Computers Techniques Engineering College of Technical Engineering The Islamic University Najaf Iraq Department of Computers Techniques Engineering College of Technical Engineering The Islamic University of Al Diwaniyah Al Diwaniyah Iraq

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

Due to their improved energy economy and reduced circuit complexity, multivalue logics have shown to be beneficial in the field of digital system design. In the field of multivalue logic, quaternary logic is typically regarded as an inventive method. In this article, the design of a quaternary to binary converter is realized by means of 18 nm FinFET technology. Further, the performance of quaternary to binary converter is examined by employing different FinFET models. Based on simulation outcomes, the LVT, SVT, and HVT FinFET models display power consumption values of 30.23, 33.89, and 27.14 µW, transient delay values of 0.27, 0.20, and 0.26 ns, and power delay product values of 8.16, 6.77 and 7.05 (X10 -15 J), respectively. The designed quaternary to binary converter architecture can be beneficial in data communication, memory systems, digital signal processing, quantum computing, error detection and correction and for applications that requires quaternary signals.

关键词： Analytical models Power demand Digital systems Biological system modeling FinFETs Energy efficiency Delays logic Integrated circuit modeling Transient analysis

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CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop Using Transmission Gate logic for Low Power VLSI applications

CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop U...

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Multi-Agent Systems for Collaborative Intelligence (ICMSCI), international conference on

作者： P. Nagarajan Lalith Kumar S Hariharan M Nitheesh S Rahul Krishnan R. Bhairavi Department of ECE SRM Institute of Science and Technology Chennai Tamilnadu India

ISBN: (数字)9798331509828

ISBN: (纸本)9798331509835

The rapid evolution of low-power applications in VLSI design calls for innovative transistor technologies that are capable of meeting stringent energy efficiency requirements. Carbon Nanotube field-Effect Transistors (CNTFETs) offer significant advantages over conventional MOSFETs, particularly in nanoscale, low-power, and high-performance circuits. This paper presents a comparative study of two Flip-Flop circuits aimed at power-efficient digital design. The first circuit, an existing design Pass Transistor logic based Implicit Pulsed - Dual Edge Triggered Flip-Flop (PTIP-DETFF) [1] which was originally implemented using MOSFET technology, has been converted into CNTFET technology to facilitate direct performance comparison. The second circuit is a novel CNTFET-based design that employs Pulse Implied Binary Edge Activated Flip-Flop (PI-BEAFF) using Transmission Gate logic, resulting in further optimization of power and delay characteristics. Simulation results reveal that the proposed CNTFET-based flip-flop, designed using 32nm technology, achieves a power reduction of approximately 99.73% and a delay reduction of 41.53%, with an average power of 5.52654 nW and delay of 8.58667 ps, compared to $2.0290 \mu\text{W}$ and 14.685 ps in the existing circuit. This analysis considers critical metrics, including Power-Delay-Product (PDP), Energy-Delay-Product (EDP), Power-Energy-Product (PEP), transistor count, and the number of clocked transistors. The results underscore the potential of CNTFET technology in realizing low-power, high-speed digital circuits, highlighting its applicability for future energy-efficient VLSI systems.

关键词： MOSFET Power demand Simulation Very large scale integration logic gates Energy efficiency CNTFETs Delays Transistors Flip-flops

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GaN Power HEMT with Breakdown Voltage >800 V Grown by MBE

GaN Power HEMT with Breakdown Voltage >800 V Grown by MBE

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Power, Energy and Electrical Engineering (CPEEE), international conference on

作者： ZC Yang YQ Wang JG Zhuang Eason Liao Research and Development Department MASSPHOTON LIMITED Hong Kong SAR China MASSPHOTON LIMITED Hong Kong SAR China

ISBN: (数字)9798331520090

ISBN: (纸本)9798331520106

We report on a GaN power HEMT with a breakdown voltage exceeding 800 V, grown by MBE on sapphire. The high breakdown voltage, surpassing 800 V, is achieved through the use of an ultra-thin AlN buffer layer grown by MBE and the implementation of a single-level gate field plate technique. The MBE technique facilitates the growth of a dopant-free buffer layer and pseudomorphic epilayers, which is advantageous for the high reliability of GaN power HEMTs. Additionally, the single-level gate field plate technique aids in reducing the overall fabrication cost and also enhances the reliability of GaN power HEMTs. These merits highlight the potential of the reported GaN power HEMT for applications in high-power electronics.

关键词： Buffer layers Fabrication Electric potential Costs Electric breakdown HEMTs logic gates Reliability III-V semiconductor materials Aluminum nitride

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