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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是131-140 订阅

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Pentacene Based Organic Tunnel field Effect Transistor for Hybrid Working Environment

Pentacene Based Organic Tunnel Field Effect Transistor for H...

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international conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

作者： Nivedha E Rajesh Agarwal Department of Electronics and Communication Engineering College of Engineering and Technology SRM Institute of Science and Technology Kattankulathur Tamilnadu India

ISBN: (数字)9798331524227

ISBN: (纸本)9798331524234

This paper proposes a compact gate Organic Tunnel field Effect Transistor (CG O-TuFET) using pentacene as semiconductor to improve the switching speed for working under hybrid (organic and inorganic) environments by analyzing its physical significance and performance. It examines crucial parameters and performs simulations using Silvaco TCAD tool. The parameters under study are same as in the Organic Thin Film Transistor (OTFT) since both works as a transistor. The observed values of CG O-TuFET are threshold voltage (V th )= -1.4 V, average subthreshold swing (SS avg )=33.33 mV/dec for 7 decades, on-current of 65.16 µA, Current ON/OFF ratio=10 14 which are significant data for applications demanding high-speed operation within hybrid organic-inorganic environments.

关键词： Wireless communication Pentacene TFETs Signal processing logic gates Organic thin film transistors Remote working Threshold voltage Transistors Switching circuits

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Design and Simulation of Broken Gate TFET and its RF applications

Design and Simulation of Broken Gate TFET and its RF Applica...

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international ECTI Northern Section conference on Electrical, Electronics, Computer and Telecommunications Engineering (ECTI-NCON)

作者： Kh. Alisha Singha Aditya Singha Swrang Brahma Karapallav Chutia Bijoy Goswami Dept. of Electronics and Telecommunication(B.Tech) Assam Engineering College JalukbariGuwahati(ASTU) Guwahati Assam India

ISBN: (数字)9798331543273

ISBN: (纸本)9798331543280

In this study, we introduce a novel Broken-Gate Tunnel field-Effect Transistor (BG-TFET) architecture based on silicon. The structure has been refined and analytically characterized. The device showcases an enhanced subthreshold slope (SS) of 19 mV/dec, minimal bidirectional current, and ON-current values on par with contemporary designs of similar dimensions. The findings of the device parameters are corroborated through the simulations of SILVACO employing the methodology of Nonlocal tunneling.

关键词： Performance evaluation Accuracy TFETs Sensitivity Tunneling Predictive models logic gates Silicon Semiconductor process modeling Transistors

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8th international Workshop on field-programmable logic and applications, FPL 1998

8th International Workshop on Field-Programmable Logic and A...

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8th international Workshop on field-programmable logic and applications, FPL 1998

ISBN: (纸本)3540649484

The proceedings contain 68 papers. The special focus in this conference is on Design Methods and General Aspects. The topics include: New CAD framework extends simulation of dynamically reconfigurable logic;a language for parametrised and reconfigurable hardware design;integrated development environment for logic synthesis based on dynamically reconfigurable FPGAs;designing for xilinx XC6200 FPGAs;perspectives of reconfigurable computing in research, industry and education;catalyst for new computing paradigms;run-time management of dynamically reconfigurable designs;acceleration of satisfiability algorithms by reconfigurable hardware;an optimized design flow for fast FPGA-based rapid prototyping;a knowledge-based system for prototyping on FPGAs;a rapid prototyping system based on java and FPGAs;prototyping new ILP architectures using FPGAs;fast floorplanning for FPGAs;a fault model for the configurable logic modules;reconfigurable hardware as shared resource in multipurpose computers;the bridge between high speed sensors and low speed computing;a reconfigurable engine for real-time video processing;an FPGA implementation of a magnetic bearing controller for mechatronic applications;exploiting contemporary memory techniques in reconfigurable accelerators;a platform for tractable virtual circuitry and reactive environment for runtime reconfiguration.

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A Study on Hardware-based Implementation of Homomorphic Encryption

A Study on Hardware-based Implementation of Homomorphic Encr...

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Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), international conference

作者： Gurdeep Singh Sonam Mittal Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (数字)9798331515911

ISBN: (纸本)9798331515928

Homomorphic encryption is an innovative cryptographic mechanism that allows performing cryptographic operations even on encoded data without intermediate decoding. As a result, sensitive information cannot be compromised in case of dealing with outsourcing services. This article firstly provides the general background of HE and most notably discusses the types of HE such as partial homomorphic encryption, somewhat homomorphic encryption, and fully homomorphic encryption Each of these types has its advantages on drawbacks depending on the type of operations and the level of computation efficiency. The paper also considers research undertaken recently oriented towards increasing the feasibility of HE by all means, especially the lowering of the costs in computation. A comparative analysis matrix contains distinctive features of various approaches in HE and defines their complexity, security, and usability concerns. This and further surveys present the HE history and its above- and below-the-line progress and suggest paths for HE-morphed developmental works for applications such as cloud computing and machine learning that are inherently privacy-preserving.

关键词： Surveys Cloud computing VHDL Costs Computer architecture Hardware Vectors History Homomorphic encryption field programmable gate arrays

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Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Yun Wu John McAllister School of Electrical Electronic and Computer Engineering Queen’s University Belfast

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using ℓ 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×.

关键词： Image coding Power demand Instruments Voltage Robot sensing systems Throughput Sensors Image reconstruction field programmable gate arrays Engines

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引用

international conference on Electronics, Information and Communications (ICEIC)

作者： Min Jung Sujin Kim Haechannuri Noh Huijin Roh Nahyeon Kim Ji-Hoon Kim dept. Division of Electronic & Semiconductor Engineering Ewha Womans University Seoul Republic of Korea

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

This paper proposes a vector similarity search acceleration by leveraging DRAM-based Processing In Memory (PIM), which is a key component in Retrieval-Augmented Generation (RAG) used to address limitations in large language models (LLM). As datasets expand, distance computations in vector similarity searches become increasingly memory-intensive. To tackle this challenge, we developed vector similarity search applications using both brute-force and Hierarchical Navigable Small World (HNSW) algorithms, with the distance computation process accelerated through PIM. The proposed PIM implementation was emulated on an FPGA board, when verification and testing demonstrated significant performance gains. These findings highlight the promising potential for PIM commercialization and its capability to enhance LLM performance.

关键词： Large language models Computational modeling Retrieval augmented generation Euclidean distance Performance gain Vectors Libraries field programmable gate arrays Commercialization Testing

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9th international Workshop on field programmable logic and applications, FPL 1999

9th International Workshop on Field Programmable Logic and A...

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9th international Workshop on field programmable logic and applications, FPL 1999

ISBN: (纸本)3540664572

The proceedings contain 65 papers. The special focus in this conference is on Signal Processing and CAD Tools for DRL. The topics include: Reconfigurable processors for high-performance, embedded digital signal processing;a linear gammatone filterbank design for a model of the auditory system;a plug-in architecture for video processing;an interpretive simulation and visualization environment for dynamically reconfigurable systems;modelling and synthesis of configuration controllers for dynamically reconfigurable logic systems using the DCS CAD framework;optimal finite field multipliers for FPGAs;memory access optimization and RAM inference for pipeline vectorization;analysis and optimization of 3-D FPGA design parameters;ultra-fast placement for FPGAs;placement optimization based on global routing updating for system partitioning onto multi-FPGA mesh topologies;hierarchical interactive approach to partition large designs into FPGAs;logical-to-physical memory mapping for FPGAs with dual-port embedded arrays;a temporal floorplanning based CAD framework for dynamically reconfigurable logic systems;a bipartitioning algorithm for dynamic reconfigurable programmable logic;self controlling dynamic reconfiguration;an internet based development framework for reconfigurable computing;on tool integration in high-performance FPGA design flows;hardware-software codesign for dynamically reconfigurable architectures;serial hardware libraries for reconfigurable designs;reconfigurable computing in remote and harsh environments;communication synthesis for reconfigurable embedded systems and run-time parameterizable cores.

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FPGA-enabled hand gesture recognition for smart home applications

FPGA-enabled hand gesture recognition for smart home applica...

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international conference on Energy, Power, Environment, Control and Computing (ICEPECC 2025)

作者： Misbah Batool Mohsin Saleem Maryam N. Khan Faisal Siddiqui Ahmed Salim Department of Electrical Engineering Namal University Mianwali Pakistan Software Development Cell Namal University Mianwali Pakistan Department of Electrical and Computer Engineering COMSATS University Islamabad Pakistan

ISBN: (数字)9781837243150

Machine learning (ML) algorithms trained with hand gesture data have achieved accuracy rates close to 95%. However, despite this high accuracy, a trained ML algorithm requires hardware implementation to be effectively utilized in practical applications. In the proposed approach, we select one of the three investigated ML algorithms (CNN, ResNet50, and MobileNetV2) that demonstrates the best accuracy and make it compatible with loading onto a field programmable Gate Array (FPGA). This allows the algorithm to be effectively utilized in real-world applications. The optimized algorithm was implemented on a Zynq 7000 board to enhance performance, achieving greater efficiency, accuracy, and lower power consumption compared to traditional CPU-based or other architectures. The implementation was tested using a custom dataset containing six distinct hand gestures for detection and computation. Resource-efficient utilization led to a 2% increase in accuracy and a 5% reduction in processing time for the CNN-trained model on the FPGA compared to the CPU. Similarly, the ResNet50-trained model on the FPGA achieved 7% higher accuracy and 9% faster processing time compared to its execution on a CPU. Hand gesture recognition integrated with FPGAs can achieve real-time responsiveness, energy efficiency, and reliability, making them ideal for resource-constrained environments that demand high performance. This demonstrates the FPGA's advantage in smart home solutions, which combine accuracy, speed, and low power consumption.

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Low Power Design Analysis of ALU Using FinFET

Low Power Design Analysis of ALU Using FinFET

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Device Intelligence, Computing and Communication Technologies, (DICCT), international conference on

作者： Sujit Suresh Akarsha Ram Aakash M Prachi Sharma School of Electronics Engineering Vellore Institute of Technology Vellore Tamil Nadu India

ISBN: (数字)9798331543358

ISBN: (纸本)9798331543365

This paper aims to provide a comparative analysis of low-power design methods for the implementation of the Arithmetic logical Unit using Fin- field Effective Transistor. The study evaluates four new important low-power methodologies: Complementary Metal Oxide Semiconductor, Gate Diffusion Input, Subthreshold and Adiabatic design. The paper aims to be the first of its kind to provide a comparative analysis using these four low-power models in FinFET Technology using the Cadence Virtuoso designing tool. FinFET, being a modern technology with lower power leakage than the conventional MOSFET, is being used in the four design models to test feasibility. These models showcase the practical implications of deploying these sophisticated models in an 8-bit Arithmetic logical unit to harness real-life use cases. The study investigates the tradeoff between the number of transistors required in each design, the power efficiency obtained, the area utilized, the delay, leakage current and the voltage transfer curve. The models are implemented in an ALU to understand how they would perform in real-world computational needs. We were able to obtain a reduction in power consumption of 76% provided by the Subthreshold Adiabatic logic ALU and a decrease of 83% in the case of GDI based ALU. The findings contribute to understanding how FinFET 7nm technology can optimize power consumption for various digital applications, with potential benefits for both high-performance and low-power domains.

关键词： Power demand Program processors Circuits Noise logic gates FinFETs Delays Transistors logic Arithmetic

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Impact of Material Variations on Gate-All-Around Nanowire FETs for Low-Power applications

Impact of Material Variations on Gate-All-Around Nanowire FE...

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Smart and Sustainable Developments in Electrical Engineering (SSDEE), IEEE international conference on

作者： Sidhant Rana Mandeep Singh Balwinder Raj Ramesh Kumar Sunkaria ECE Dept. Nanoelectronics Research Lab ECE NIT Jalandhar India

ISBN: (数字)9798331542108

ISBN: (纸本)9798331542115

The present research resolves scaling problems in advanced technology nodes by designing and analyzing high-k dielectric Gate-All-Around (GAA) silicon nanowire field-Effect Transistors (FETs). GAA FETs are ideal for sub-5 nm nodes because they offer superior electrostatic control and less short-channel effects than conventional planar and FinFET designs. The ability of high-k dielectrics, such SiO 2 , HfO 2 , and BaTiO 3 , to achieve maximum gate capacitance while minimizing leakage currents is being studied. Subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are significantly improved in GAA FETs with HfO 3 and BaTiO 3 through careful tuning of device design, including channel length and nanowire diameter, as the study shows. These improvements show how GAA designs and high-k materials may be employed to enhance device performance and scalability.

关键词： Performance evaluation Silicon compounds Gallium arsenide field effect transistors logic gates Nanoscale devices Dielectrics Hafnium compounds High-k dielectric materials Leakage currents

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