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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是141-150 订阅

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Novel Hardware Architectures for PRESENT Block Cipher and its FPGA Realizations

Novel Hardware Architectures for PRESENT Block Cipher and it...

引用

international conference on VLSI Design

作者： Ruby Mishra Manish Okade Kamalakanta Mahapatra School of Electronics Kalinga Institute of Industrial Technology Bhubaneswar India Dept. of ECE National Institute of Technology Rourkela India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

The paper investigates novel hardware architectures for PRESENT Block Cipher with the motivation of its applicability to IoT applications. PRESENT has been chosen for two reasons: firstly, it belongs to the lightweight cipher category, and secondly, existing works haven't fully focused their attention on power metric optimization of this cipher. The Substitution Permutation Network (SPN) module of PRESENT cipher is optimized by modifying its datapath and utilizing additional hardware units that significantly reduce power consumption and achieve high throughput. The novel aspect of the SPN module design is the input selection and feeding technique to the substitution and permutation layers via the hardware units comprising multiplexers. The optimized SPN module is then included in the overall encryption architecture of PRESENT for performance analysis. The proposed architectures have been evaluated on NEXYS4 DDR FPGA at an RFID operating frequency of 13.56 MHz, making them suitable for IoT applications. Additionally, the paper also throws light on how a designer can optimally harness the resources available in an FPGA architecture to achieve improvement in the performance of the cipher architecture. Comparative analysis with state-of-the-art shows dynamic power reduction by 28.57% and a reduction of 32.81% in the area for the proposed architectures. Besides, performance parameters like the throughput of the proposed design have been significantly improved while maintaining an optimized energy consumption when compared with state-of-the-art architectures.

关键词： Measurement Ciphers Power demand Very large scale integration Throughput Hardware Performance analysis Internet of Things Optimization field programmable gate arrays

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Integrating Fuzzy logic and Morphological Edge Detection for Enhanced UAV Orthomosaic Mapping

Integrating Fuzzy Logic and Morphological Edge Detection for...

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Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), IEEE conference on

作者： Pallavi Singh Nagesh K N Neerav Sharma Department of Electronics and Communication Engineering Nagarjuna College of Engineering and Technology Bengaluru India IIT Roorkee Development Foundation Indian Institute of Technology Roorkee Roorkee India

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

The field of engineering is undergoing continuous advancements aimed at optimizing efficiency and precision. Surveying and mapping, fundamental components of Geomatics engineering, have evolved significantly with the adoption of advanced technologies. Among these, ‘Unmanned Aerial Vehicles (UAVs)’ have been a spotlighted tool for conducting precise and efficient surveying and mapping. This study leverages UAV-acquired data to generate high-resolution point clouds and three-dimensional textured mesh models, forming the basis for Orthomosaic imagery creation. The research highlights critical challenges encountered during the generation and analysis of Orthomosaic images, emphasizing the need for image correction and enhancement to achieve application-level precision in accurate mapping and monitoring. To address these challenges, the study integrates Fuzzy logic and advanced Edge Detection techniques in image processing to enhance the quality and accuracy of Orthomosaic imagery. The findings provide valuable insights into the methodologies and outcomes of the proposed approach, demonstrating its potential to significantly improve the precision and efficiency of Orthomosaic applications. Furthermore, this research underscores the broader implications for engineering and environmental studies, paving the way for more effective and innovative solutions in these domains.

关键词： Fuzzy logic Point cloud compression Technological innovation Solid modeling Geomagnetism Accuracy Image edge detection Autonomous aerial vehicles Monitoring Image enhancement

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Hardware Accelerators for Deep Learning applications

Hardware Accelerators for Deep Learning Applications

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IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Gaurav Tiwari Sangeeta Nakhate Alok Pathak Abhinandan Jain Shardul Penurkar Electronics and Communication MANIT Bhopal Computer Science VIT Vellore

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

Deep neural networks (DNNs) are essential for AI applications like computer vision, medical diagnosis, and autonomous vehicles, due to their exceptional performance. However, as DNN models grow increasingly complex, they demand substantial computational power that general-purpose processors struggle to provide. To meet these needs, domain-specific hardware accelerators, including GPU-based, TPU-based, in-memory, FPGA, and ASIC-based accelerators, have been developed. GPU-based accelerators, such as those from NVIDIA, excel in parallel processing, making them ideal for large-scale computations. TPU-based accelerators, optimized by Google for machine learning, offer impressive speed and efficiency. In-memory accelerators overcome memory bottlenecks by storing data close to computation units, enhancing data access speed. FPGA-based accelerators can be highly customized for specific tasks, while ASIC-based accelerators, tailored for specific applications, deliver the highest performance and energy efficiency, albeit at a higher development cost. This paper reviews the necessity of these accelerators, their types, and their potential impact on the future of AI technology.

关键词： Reviews Electron accelerators Graphics processing units Artificial neural networks Parallel processing Energy efficiency Internet Medical diagnosis Hardware acceleration field programmable gate arrays

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field-programmable logic: Architectures, Synthesis, and applications : 4th international Workshop on field-programmable logic and Applicaitons, Fpl '94, Prague, Czech Republic, September 7-9, 1994 : Proceedings

Field-Programmable Logic: Architectures, Synthesis, and Appl...

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1994年

作者： Michal Servít Reiner W Hartenstein

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7th international Workshop on field-programmable logic and applications, FPL 1997

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7th international Workshop on field programmable logic and applications, FPL 1997

ISBN: (纸本)3540634657

The proceedings contain 51 papers. The special focus in this conference is on Devices and Architectures. The topics include: Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor;CAD-oriented FPGA and dedicated CAD system for telecommunications;a three dimensional FPGA architecture, its fabrication, and design tools;extending dynamic circuit switching to meet the challenges of new FPGA architectures;performance evaluation of a full speed PCI initiator and target subsystem using FPGAs;implementation of pipelined multipliers on xilinx FPGAs;the XC6200DS development system;thermal monitoring on FPGAs using ring-oscillators;a reconfigurable approach to low cost media processing;a flexible platform for codesign and dynamic reconfigurable computing research;stream synthesis for a wormhole run-time reconfigurable platform;pipeline morphing and virtual pipelines;parallel graph colouring using FPGAs;run-time compaction of FPGA designs;partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement;a case study of partially evaluated hardware circuits;run-time parameterised circuits for the xilinx XC6200;automatic identification of swappable logic units in XC6200 circuitry;towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic;exploiting reconfigurability through domain-specific systems;technology mapping by binate covering;a new packing, placement and routing tool for FPGA research;technology mapping of heterogeneous LUT-based FPGAs and technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs.

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6th international Workshop on field-programmable logic and applications, FPL 1996

6th International Workshop on Field-Programmable Logic and A...

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6th international Workshop on field-programmable logic and applications, FPL 1996

ISBN: (纸本)9783540617303

The proceedings contain 50 papers. The special focus in this conference is on High-level Design I, New Software and Hardware Development Tools. The topics include: Portable pipeline synthesis for FCCMs;a framework for developing parametrised FPGA libraries;co-evaluation environment for FPGA architecture and CAD system;an universal CLA adder generator for SRAM-based FPGAs;a data driven computer on a virtual hardware;custom computing machines vs. hardware/software codesign;reconfigurable and adaptive computing environment;computing 2-D DFTs using FPGAs;computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping;architectural synthesis and efficient circuit implementation for field programmable gate arrays;reconfigurable pipelined datapath;solving satisfiability problems on FPGAs;FPGA implementation of the block-matching algorithm for motion estimation in image coding;parallel CRC computation in FPGAs;coherent demodulation with FPGAs;the trianus system and its application to custom computing;flexible codesign target architecture for early prototyping of CMIST systems;a reconfigurable multiprocessor testbed;a slow motion engine for the analysis of FPGA-based prototypes;implementing reconfigurable datapaths in FPGAs for adaptive filter design;a fast constant coefficient multiplier for the XC6200;key issues for user acceptance of FPGA design tools;reconfigurable DSP demonstrators for the development of spacecraft payload processors;reconfigurable logic based fibre channel network card with sub 2 micro-second raw latency;an instruction-level custom-configurable processor;architectural synthesis techniques for dynamically reconfigurable logic and fast reconfigurable crossbar switching in FPGAs.

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11th international conference on field-programmable logic andapplications 2001

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11th international conference on field-programmable logic and applications, FPL 2001

ISBN: (纸本)3540424997

The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: Technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based FPGAs;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS FPGAs;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmable logic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for FPGAs;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of field programmable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for FPGAs;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.

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Emotional Intelligence in Chatbots: A Study on Enhancing User Experience with Llama3 and Ollama

Emotional Intelligence in Chatbots: A Study on Enhancing Use...

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Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), IEEE conference on

作者： Salini Suresh Rachna Rathore Shailendra Thapliyal Ajith Sundaram Saloni Bansal Kabir Gaba Dept. of Mathematics Jiwaji University Gwalior India Dept. of Management Uttaranchal University Dehradun India Dept. of Business Amrita Vishwa Vidyapeetham Kochi India Dept. of Computer Eng. & Applications GLA University Mathura India Dept. of CSE (AIML) CSE-APEX Chandigarh University Chandigarh India

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

The field of emotional support chatbots has become a significant part of the tools designed to enhance mental well-being through human-like conversations. This paper introduces an innovative approach that prioritizes empathy and context continuity. The proposed solution, named "SOLARA" utilizes the Llama3.2:3b model within the Ollama framework. By incorporating sentiment analysis powered by fuzzy logic, SOLARA delivers context-aware, personalized, and empathetic responses. The Llama3.2:3b model enhances SOLARA’s ability to understand complex language and retain memory more effectively. With Ollama enabling offline functionality, SOLARA ensures user privacy and reliability. Compared to existing solutions, this approach demonstrates improvements in emotional accuracy, response quality, and conversational coherence. The solution highlights the potential of NLP in addressing emotional concerns while balancing performance and user privacy, paving the way for further exploration in this field.

关键词： Fuzzy logic Privacy Sentiment analysis Technological innovation Accuracy Coherence Mental health Chatbots User experience Reliability

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FPGA Implementation of Sparse Matrix Vector Multiplication with Small-Scale Matrix Element Router

FPGA Implementation of Sparse Matrix Vector Multiplication w...

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IEEE international conference on Consumer Electronics (ICCE)

作者： Ryosuke Yanangisawa Kenji Kanazawa University of Tsukuba Tsukuba Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Sparse Matrix Vector multiplication (SpMV) is a fundamental operation in various computational science applications, characterized by a significant degree of inherent parallelism. Recent FPGA-based SpMV accelerators employ routing architectures such as crossbar switch or 2D-mesh network-on-Chip (NoC) to efficiently map matrix non-zero elements to their corresponding vector elements. The scale of these routing archi-tectures, however, serves as a key constraint on the attainable parallelism in FPGA-based SpMV accelerators. In this paper, we describe two approaches aimed at reducing the size of NoCs to exploit greater parallelism while suppressing the increase of hardware resource usage. In a previous work, each node in NoCs equipped multiple elastic buffers to prevent routing stalls, which was the main factor to increased resource usage. Our first approach replaces the elastic buffers to simple data registers to minimize the circuit size, while the second approach introduces ping-pong buffering to improve routing performance. Experimental results show that our approaches achieve 1.3 × to 1.7 ×throughput improvement over the previous work with less increase of resource usage.

关键词： Scientific computing Switches Network-on-chip Parallel processing Routing Vectors Hardware Registers Sparse matrices field programmable gate arrays

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Multi-label Emotion Classification using modified Sequential Deep Learning Architecture for Speech Emotion Recognition

Multi-label Emotion Classification using modified Sequential...

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Artificial Intelligence and Data Engineering (AIDE), international conference on

作者： Akshar Samudrala Adithya Santhosh Dhruv Bavaria M Srinivas School of Computing Amrita Vishwa Vidyapeetham Amaravati India

ISBN: (数字)9798331527518

ISBN: (纸本)9798331527525

In recent years, audio classification has gained significant attention due to its wide range of applications, particularly in the field of Speech Emotion Recognition (SER). Our paper presents a unique approach to multi-label audio classification based on emotion using a modified Sequential Deep Learning architecture, applied to a combined dataset of TESS, RAVDESS, SAVEE, and CREMA-D datasets. Our model employs SoftMax to obtain multi-class probabilities, which are then used to calculate evaluation metrics and uncertainties. Additionally, we explore the performance of our model across various emotion categories, demonstrating its robustness and versatility. Our model used Dropout Layers after every Layer in the architecture to decrease the overfitting and increase the accuracy. Comprehensive experiments show that our model achieves state-of-the-art results in multi-label classification, outperforming previous methods. The method also extensively evaluates the model’s performance.

关键词： Measurement Emotion recognition Accuracy Uncertainty Deep architecture Speech recognition Probabilistic logic Data models Robustness Overfitting

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