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Trends in Material Science and Inventive Materials (ICTMIM), international conference on

作者： Y Sri Rama E Vijaya Babu K V Balaramakrishna Sanjana Mohithe Siri Chandana Prodduturi Bhoomika Amgoth Department of ECE Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering & Technology Hyderabad India Department of ECE Aditya University Surampalem India

ISBN: (数字)9798331501488

ISBN: (纸本)9798331501495

Efficient filtering methods in contemporary radar systems are needed to process high-frequency signals with little distortion and noise. The Cascaded Integrator-Comb filter has a popular choice for decimation and interpolation because of its easy hardware implementation and low complexity. The focus of this project is the VLSI implementation and simulation of a 100 MHz Cascaded Integrator-Comb filter for real-time radar *** CIC filter is implemented using Verilog HDL and simulated in Xilinx Vivado for the evaluation of important performance characteristics like latency, power consumption, and resource consumption. The architecture includes cascaded integrator and comb stages that efficiently suppress the aliasing effects and improve the signal quality. The simulation outputs confirm the behavior and effectiveness of the CIC filter in the processing of high-speed radar signals with signal *** VLSI design methodologies, the project presents an efficient and hardware-friendly solution for real-time radar signal processing. The research proves that high-speed digital filtering can be implemented in ASIC or FPGA-based radar systems, and it advances VLSI-based signal *** current version maintains VLSI simulation in Xilinx Vivado as the central theme and steers clear of FPGA implementation while still taking on real-time applications.

关键词： Power demand Filtering Very large scale integration Radar signal processing Real-time systems System-on-chip Radar applications Digital filters Junctions field programmable gate arrays

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Energy-Efficient Stochastic Computing Architectures for Neural Network Performance in FPGA Systems

Energy-Efficient Stochastic Computing Architectures for Neur...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： A.Dinesh Babu C. Gomathy Department of Electronics and Communication Engineering Faculty of Engineering and Technology SRM Institute of Science and Technology Chennai India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

This paper presents an energy-efficient stochastic computing (SC) architecture tailored for neural network applications on FPGA platforms. The proposed architecture integrates a Bayesian neural network (BNN) computation unit with a novel hybrid stochastic number generator (SNG) that combines Linear Feedback Shift Registers (LFSRs) and Halton sequences. This hybrid approach enhances the quality of generated bit-streams, significantly reducing correlation and improving the accuracy of SC-based computations. Stochastic computing allows complex arithmetic operations to be performed using simple logical gates, reducing hardware complexity and power consumption. Bayesian neural networks, due to their probabilistic framework, align well with the random nature of SC, allowing for resilient and efficient computations in resource-constrained environments. Experimental evaluations were conducted on an FPGA, measuring power consumption, computational accuracy, and resource utilization across varying bit-stream lengths. Results indicate that the proposed architecture achieves approximately 25% lower power consumption compared to conventional SC-based neural network implementations, with an improvement in mean squared error (MSE) accuracy. This energy efficiency and accuracy make the architecture particularly suitable for embedded systems, IoT devices, and other applications requiring low-power, high-performance neural network solutions. The proposed design offers a scalable solution for future neural network implementations in energy-constrained environments, contributing to advancements in sustainable hardware design.

关键词： Accuracy Power demand Neural networks Stochastic processes Computer architecture Energy efficiency Hybrid power systems Hardware Computational efficiency field programmable gate arrays

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High frequency Area efficient architecture of lightweight authenticated encryption algorithm GIFT-COFB for resource-constrained IOT devices

High frequency Area efficient architecture of lightweight au...

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Power, Control and Computing Technologies (ICPC2T), conference on

作者： PankajKu Choubey Bijayananda Patnaik Bibhudendra Acharya Department of Electronics and Communication Engineering National Institute of technology Raipur Chhattisgarh India

ISBN: (数字)9798331530402

ISBN: (纸本)9798331530419

Safe and efficient cryptography solutions which may perform in the limitation of resources situations like Internet of Things systems etc is increasingly required, because the IoT continues to expand. These issues are resolved by lightweight cryptography, which minimizes memory and processing requirements while offering robust security. The necessity of cipher that strike an equilibrium between protection and sustainable use of resources is highlighted by the Internet of Thing’s explosive growth. Because of its resilience and effective design, the GIFTCOFB cipher stands out as a dependable choice. This work investigates the development of a high-frequency low area hardware architecture that speeds up the GIFT-COFB encryption in order to meet the performance needs of Internet of Things applications. Several FPGA boards have been used to model and implement the suggested high-frequency design, among them, the best results for maximum working freq, latency and area have been achieved in the seven series of Vertex and Kintex boards.

关键词： Ciphers Memory management Side-channel attacks Ubiquitous computing Throughput Hardware Robustness Encryption Internet of Things field programmable gate arrays

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Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs

Physical Insights into the Leakage Mechanisms Governing the ...

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international conference on VLSI Design

作者： Jaspreet Singh Aakash Kumar Jain M. Jagadesh Kumar Department of Electrical Engineering IIT Delhi New Delhi

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

The lateral Band-to-band tunneling (L-BTBT) has been extensively studied in Silicon Junctionless field effect transistors (JLFETs) as the dominant leakage mechanism. However, the same analysis does not hold true for wide bandgap materials like 4H-SiC, since as the recent studies show, for lower drain bias the L-BTBT is not triggered in 4H-SiC JLFETs. Therefore, in this paper, for the first time, we present a comprehensive analysis of the various leakage mechanisms governing the subthreshold performance of the 4H-SiC based ultra-short channel planar junctionless (JL) FETs. Using well-calibrated 2-D device simulations, our study gives physical insights into the three main leakage components in JLFETs: i) Gate induced drain leakage (GIDL) mechanism ii) direct gate tunneling, and (iii) inefficient volume depletion. Unlike the silicon-based JLFETs which are significantly impacted by the L-BTBT induced GIDL, the 4H-SiC JLFETs are quite immune to the L-BTBT induced GIDL due to their wider bandgap compared to the silicon. However, the leakage mechanism in 4H-SiC can essentially be dictated either by the gate leakage due to the direct tunneling through the thin gate dielectric or the inefficient volume depletion especially for the sub-10 nm regime. Therefore, we have presented the design guidelines for sub-10 nm regime, which can be used for designing required channel length, channel thickness, and gate oxide thickness to have the effective volume depletion. Our comprehensive analysis reveals essential findings that can help in developing and adopting the 4H-SiC based JLFETs at advanced technology nodes, especially for low power and low leakage applications, like Internet of Things (IoT) and automotive applications.

关键词： Photonic band gap Design methodology field effect transistors logic gates Very large scale integration Silicon Threshold voltage Gate leakage Dielectrics Internet of Things

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Design of a 16-Bit Power-Efficient Posit Multiplier with Selective Activation and Modified Radix-4 Booth Multiplier

Design of a 16-Bit Power-Efficient Posit Multiplier with Sel...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： T V S Adinarayana G Rajesh Yashasvi Linga Reddy Vishwass R Yadav Srinivas Abhinay Gandla Electronics and Communication Engineering New Horizon College of Engineering Bangalore India Electrical and Electronics Engineering New Horizon College of Engineering Bangalore India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

The Posit number system presents a more flexible and precise alternative to the traditional IEEE 754 floating-point format, but its inherent complexity, particularly in multiplication, can lead to high power consumption in hardware implementations. This research proposes a power-efficient design for a 16-bit Posit multiplier that uses a modified Radix-4 Booth algorithm to selectively activate only the necessary sections of the multiplier based on the required bit-width for the mantissa. By minimizing unnecessary computations and switching activities, the design reduces dynamic power consumption. The architecture includes components such as the mantissa multiplication unit, normalization stage, and rounding unit, all optimized for efficiency. Simulation results using Xilinx Vivado confirm the functionality of the design, while power and area analysis on the Xilinx Artix-7 FPGA demonstrate its efficiency compared to existing implementations. The proposed design is suitable for low-power applications and offers significant improvements in both power consumption and area utilization.

关键词： Power demand Program processors Simulation Heuristic algorithms Switches Computer architecture System-on-chip Informatics field programmable gate arrays Mobile computing

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Efficient FPGA Architecture for DPDK Flow Rules Processing

Efficient FPGA Architecture for DPDK Flow Rules Processing

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international conference on Advanced Communication Technology (ICACT)

作者： Vo Thanh Van Nguyen Phu Lam Nguyen Nhat Truong Nguyen Quang Phuong Vu Tuan Duc Le Ngoc Toan Viettel High Technology Industries Corporation Viettel Group Vietnam

ISBN: (数字)9791188428137

ISBN: (纸本)9798331507602

With the development of the Internet, the number of connected devices and the amount of transferred data increase annually leading to more complex network applications and limitations in data processing speed. The Data Plane Development Kit (DPDK) addresses these challenges by optimizing packet processing for high-speed network applications, including offloading processing tasks to Network Interface Cards (NICs) hardware using the rte_flow interface, which allows configuration of NICs offloads with specific flow rules. However, with the increasing complexity of network applications, the number of rules used is also growing rapidly, and more complexity. This presents a challenge for building and developing network systems capable of efficiently handling a large number of rules. This paper presents an architecture for processing the rte_flow interface using FPGA-based Smart NICs to leverage the reprogrammable capabilities of hardware accelerators. The architecture uses Ternary Content-Addressable Memory (TCAM) to reduce the key size in the rule tables, significantly increasing the number of rules and rule tables supported by the FPGA. Additionally, a custom DPDK driver (named VTL driver) is developed to manage and implement algorithms aimed at optimizing the number of rules in the hardware. To evaluate our proposed architecture, the Alveo U200 FPGA-based accelerator card is used to implement these features including 8 receive rule tables and 1 transmit rule table per ethernet port. Each table supports up to 2048 wildcard matches and 16384 exact match entries. The system achieves a network throughput of 100 Gbps per port and a rule insert rate of 204 million rules per second. These results significantly enhance hardware acceleration efficiency in networking.

关键词： Performance evaluation Technological innovation Architecture Ethernet Throughput Solids Complexity theory field programmable gate arrays Hardware acceleration Network systems

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Design Innovations in TFETS: Enhancing Performance and Sensitivity Through Charged Plasma, Dual-Gate, and Work Function Techniques

Design Innovations in TFETS: Enhancing Performance and Sensi...

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Device Intelligence, Computing and Communication Technologies, (DICCT), international conference on

作者： Kaushal Kumar Challa Harshavardhan Reddy Dasari Ramesh Babu Vinay Kumar Ajay Kumar Aditya Jain ECE Department Graphic Era Deemed to be University Dehradun India ECE Department Jaypee Institute of Information Technology Noida India Symbiosis Institute of Technology Symbiosis International (Deemed University) Pune India

ISBN: (数字)9798331543358

ISBN: (纸本)9798331543365

In recent years, Tunnel field-Effect Transistors (TFETs) have garnered considerable attention as promising candidates to achieve the new generation of electronics that require high performance, low power, and scalability as they can provide increased energy efficiency due to the band-to-band tunneling (BTBT) mechanism and have a steep subthreshold slope. Nonetheless, the standard TFETs suffer from low on-state current along with short-channel effects and processing difficulties. However, to exploit these emerging potentials and improve TFET performance and capabilities junction less TFET, dual material gate, heterojunction architectures and driven work-function engineering innovations have arisen creating room for the use of TFETs in biosensing applications as well as high-frequency circuit designs. This review highlights four of the most significant advancements that comprise: Junction less and Core-Shell Nanotube TFETs for high-sensitivity detection of label-free biomolecules, Dual- Material Gate Heterojunction TFETs for enhanced on current and switching speeds, Symmetric Double-Gate Charge Plasma TFETs for simplified doping-less fabrication, and Drain Work Function Engineered TFETs to enable ambipolar suppression and improve RF performance. We then analyze the structure, functions, and applications as well the tradeoffs in terms of scalability, stability and reliability for each design.

关键词： Radio frequency Performance evaluation Technological innovation TFETs logic gates Tunneling Heterojunctions Plasmas Leakage currents Transistors

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Optimizing Regenerative Braking in Electric Vehicle: A Comprehensive Study of Control Strategies and Energy Recovery

Optimizing Regenerative Braking in Electric Vehicle: A Compr...

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Industrial Electronics: Developments & applications (ICIDeA), IEEE international conference on-

作者： Aniruddha Bhat Akash Suryawanshi Om Jadhav Sayali Jawale Dept. of Electrical Engineering JSPM's Rajarshi Shahu College of Engineering Pune Dept. of Electrical Engineering JSPM's Rajarshi Shahu College of Engineering Pune

ISBN: (数字)9798331533205

ISBN: (纸本)9798331533212

This study investigates the concept of regenerative braking in electric vehicles (EVs) and electric multiple units (EMUs), focusing on simulation and hardware in the loop (HIL) testing. This study analyses the power variation between non regenerative and regenerative braking modes, emphasizing the optimization of energy recovery and efficient power distribution. A two-stage control strategy that integrates field-oriented control for speed regulation and a DCDC converter for managing power between a battery and an ultracapacitor in a hybrid energy storage system (HESS) is proposed. The proposed system was validated through MATLAB simulations and HIL experiments, which demonstrated enhanced energy recovery, efficient load balancing, and improved battery protection. In addition, this study introduces a Mamdani fuzzy inference system for optimizing regenerative braking in fuel cell buses, considering safety, driving dynamics, and occupant comforts. The design of robust H∞ controllers further ensure system stability and minimizes disturbances during regenerative braking. The experimental results show that the H∞ controller outperforms traditional PI controllers in terms of energy recovery and dynamic response under various driving conditions. This study contributes to the advancement of regenerative braking technologies, offering insights into power system stabilization and energy conservation for both EVs and EMUs.

关键词： Fuzzy logic PI control Power system dynamics Power system stability Supercapacitors Stability analysis Hardware Batteries MATLAB Vehicle dynamics

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FPGA programmable logic block evaluation using quantified Boolean satisfiability

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 165-172页

作者： Ling, A. C. Singh, D. P. Brown, S. D. Univ Toronto Toronto ON M5S 3G4 Canada Altera Toronto Technol Ctr Toronto ON M5S 1S4 Canada

A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. This technique is general enough to be applied to any type of logic function and programmable circuit;thus, it has many applications to FPGAs. The application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.

关键词： logic synthesis field programmable gate arrays Formal logic logic functions

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Optimization of Memory Usage in High-Speed Cameras using FPGA

Optimization of Memory Usage in High-Speed Cameras using FPG...

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Electronics and Renewable Systems (ICEARS), international conference on

作者： Kavin Kumar K Neelam Sanjeev Kumar Senthilkumar C Velmurugan V G Sangar Gokul Chandrasekaran Department of Electronics and Communication Engineering Kongu Engineering College Erode India Department of Computer Science and Engineering (E.Tech.) SRM Institute of Science and Technology Chennai India Department of Electronics and Communication Engineering SIMATS Engineering SIMATS University Chennai Tamil Nadu Department of Electronics and Communication Engineering Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology Chennai Tamilnadu India Department of Computer Science and Engineering SRM Institute of Science and Technology Chennai India Department of Electronics and Communication Engineering Karpagam Institute of Technology Coimbatore India

ISBN: (数字)9798331509675

ISBN: (纸本)9798331509682

High-speed cameras generate large amounts of data, making memory optimization difficult for real-time processing. This project minimizes data size by converting RGBA (Red, Green, Blue, Alpha) images to RGB, eliminating the Alpha channel to reduce memory usage. The captured images are provided as input to Verilog code in hexadecimal format, with the conversion done by MATLAB. Bilinear Interpolation is applied to reduce the potential quantization errors during the conversion, using the values of four surrounding pixels to smooth the image and maintain quality. After processing, the image is reconstructed using MATLAB, ensuring the integrity of the output. By utilizing the parallel processing capabilities of FPGAs, this method ensures real-time performance while optimizing memory usage. It is ideal for high-speed imaging applications where both efficiency and image quality are crucial.

关键词： Interpolation Renewable energy sources Quantization (signal) Memory management Parallel processing Cameras Real-time systems MATLAB field programmable gate arrays Optimization

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