The proceedings contain 46 papers. The special focus in this conference is on Architectures;Platforms;Tools;Arithmetic and Signal Processing. The topics include: The Design of a New FPGA Architecture;Migraton of a Dua...
ISBN:
(纸本)3540602941
The proceedings contain 46 papers. The special focus in this conference is on Architectures;Platforms;Tools;Arithmetic and Signal Processing. The topics include: The Design of a New FPGA Architecture;Migraton of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process;Self-Timed FPGA Systems;XC6200 Fastmap ™ Processor Interface;The Teramac Configurable Computer Engine;Telecommunication-Oriented FPGA and Dedicated CAD System;A Configurable logic Processor for Machine Vision;Extending DSP-Boards wih FPGA-Based Structures of Interconnection;High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform;Using FPGAs as Control Support in MIMD Executions;Customised Hardware Based on the REDOC III Algorithm for High-Performance Date Ciphering;Using Reconfigurable Hardware to Speed up Product Development and Performance;Creation of Hardware Objects in a Reconfigurable Computer;Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs;Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs;Some Notes Qn Power Management on FPGA-Based Systems;An Automatic Technique for Realising User Interaction Processing in PLD Based Systems;The Proper Use of Hierarchy in HDL-Based High Density FPGA Design;Compiling Regular Arrays onto FPGAs;Compiling Ruby into FPGAs;The CSYN Verilog Compiler and Other Tools;A VHDL Design Methodolgy for FPGAs;VHDL-Based Rapid Hardware Prototyping Using FPGA Technology;Integer Programming for Partitioning in Software Oriented Codesign;Test Standard Serves Dual Role as On-Board Programming Solution;Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.
This study investigates the impact of different gate dielectric structures on the performance of charge plasma vertical tunnel field-effect transistors (TFETs). Three TFET configurations were considered: a single mate...
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ISBN:
(数字)9798331527495
ISBN:
(纸本)9798331527501
This study investigates the impact of different gate dielectric structures on the performance of charge plasma vertical tunnel field-effect transistors (TFETs). Three TFET configurations were considered: a single material gate (H fo2), a double material gate (H fO2, SiO2), and a stacked gate (H fO2 stacked on Si O2 ). All of the three structures are evaluated using lateral and vertical conduction currents, electron and hole mobilities, and quasi-Fermi levels. The results indicate a major improvement in the devices' performance with the presence of extra dielectric layers in the double and stacked gate structure. The proposed structures allow peak currents, superior carrier mobilities, as well as even more favorable tunneling barriers when compared to the single material gate. The findings suggest that the careful engineering of gate dielectric materials and their stacking can optimize the performance of TFETs, paving the way for their potential applications in future high-performance electronic devices.
High-resolution photon-counting optical time-domain reflectometry (PC-OTDR) is crucial for the development of fiber-optic sensing and network diagnostics, allowing accurate fault location and long-haul performance opt...
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ISBN:
(数字)9798331531836
ISBN:
(纸本)9798331531843
High-resolution photon-counting optical time-domain reflectometry (PC-OTDR) is crucial for the development of fiber-optic sensing and network diagnostics, allowing accurate fault location and long-haul performance optimization. A major step forward for OTDR is reported by combining a superconducting nanowire single-photon detector (SNSPD) with a low-cost FPGA-based time-to-digital converter (TDC) to perform high-resolution measurements over 150 km of fiber. The SNSPD has 63% efficiency at 1550 nm and 25 ps timing jitter in free running, and the FPGA-TDC system provides high time precession 17.0 ± 1.3 ps with high data acquisition data rates The experimental data exhibit a 22.87 dB dynamic range with 7.5 cm (25 km) and 1.6 m (100 km) spatial resolution, which reflects the high-fidelity fiber characterization capability of the system. This work lays the groundwork for future developments in real-time signal processing and automatic failure detection in fiber networks, enhancing optical sensing applications.
The main objective of this project is to design and implement a Fast Fourier Transform (FFT) IP core. Due to its ability to provide accurate frequency domain analysis of time domain signals, the FFT technique is indis...
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ISBN:
(数字)9798331529833
ISBN:
(纸本)9798331529840
The main objective of this project is to design and implement a Fast Fourier Transform (FFT) IP core. Due to its ability to provide accurate frequency domain analysis of time domain signals, the FFT technique is indispensable in many applications related to digital signal processing. The implementation is based on the radix-2 method, whose lower computational complexity and hardware resource efficiency make it a good fit for FPGA platforms. With its robust FPGA and ARM CortexA53 processors, the ZCU104 board provides an adaptable environment for creating unique IP cores and incorporating them into more complex *** objective of this project is to use the Zynq SoC’s hardware acceleration capabilities to improve the FFT core for speed and resource consumption. The ZCU104 board is used to test and validate the built IP core, proving its usefulness for real-time signal processing applications. As compared to software-based FFT implementations, the results demonstrate a notable boost in performance, underscoring the potential of FPGA based solutions in high performance computing jobs.
Fully connected (FC) layers present a significant bottleneck in the throughput of Convolutional Neural Networks (CNNs) and Transformers when deployed on hardware accelerators such as FPGAs, ASICs, and analog AI chips....
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ISBN:
(数字)9798331518752
ISBN:
(纸本)9798331518769
Fully connected (FC) layers present a significant bottleneck in the throughput of Convolutional Neural Networks (CNNs) and Transformers when deployed on hardware accelerators such as FPGAs, ASICs, and analog AI chips. This paper proposes a novel approach to mitigate this limitation by replacing FC layers with sparse graph embedding techniques derived from Low-Density Parity-Check (LDPC) codes, enabling robust weight compression. Using VGG16 as a case study, we demonstrate that our method reduces the parameters in the FC layers from 123,642,856 to just 64,000-a 1,931-fold reduction-while maintaining high-precision classification performance. Following aggressive pruning (72% weight reduction), our LDPC-based embeddings, combined with 8-bit fixed-point quantization, achieve an accuracy of 70.21%, compared to 70.89% achieved by unpruned float32. On the Xilinx Alveo U50 platform, this translates to processing up to 1119 images per second with parallel computation of 64-dimensional embeddings. Moreover, by replacing the top FC layers with the proposed graph embedding method and leveraging fast analog feature extraction (via supervised or random projections), our approach demonstrates the potential to achieve peak performance on the Alveo U50 of 4.8 million images per second for float32 100-class classification and 39.86 million images per second for 10-class classification using 16-bit fixed-point representation. These findings underscore the capability of graph embeddings to significantly enhance DNN efficiency on data center and resource-constrained edge AI hardware platforms. We hypothesize that exploiting the inherent sparsity of graph embeddings, combined with the energy efficiency of analog computation for feature extraction, can yield substantial reductions in CNN, Transformer and Diffusion DNN inference power consumption, potentially surpassing GPU efficiency by three to four orders of magnitude. This paper presents preliminary results and outlines directions for
The expansion of the FPGA into complex market sectors imposes new demands on the security model of the devices. This demonstration shows off a series of tools developed to decode and scan the contents of a bitstream f...
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ISBN:
(纸本)9781665473903
The expansion of the FPGA into complex market sectors imposes new demands on the security model of the devices. This demonstration shows off a series of tools developed to decode and scan the contents of a bitstream for malicious designs.
In this paper we present a framework for the seamlessly utilization of hardware accelerators in heterogeneous SoCs that are used to speedup the processing of Spark data analytics applications.
ISBN:
(纸本)9789090304281
In this paper we present a framework for the seamlessly utilization of hardware accelerators in heterogeneous SoCs that are used to speedup the processing of Spark data analytics applications.
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