The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained field-programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been ...
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ISBN:
(纸本)9781665437592
The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained field-programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance Computing (HPC), since single-core and multicore systems may soon hit scaling limits.
FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. The Hastlayer project aims to give a tool to software developers familiar with the...
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ISBN:
(纸本)9781467381239
FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. The Hastlayer project aims to give a tool to software developers familiar with the. NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, yielding faster program execution and lower power consumption.
Floating point arithmetic is used extensively in many applications across multiple market segments. While high performance IEEE754 floating point cores are available for FPGAs, a large datapath consisting of multiple ...
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ISBN:
(纸本)9781424419609
Floating point arithmetic is used extensively in many applications across multiple market segments. While high performance IEEE754 floating point cores are available for FPGAs, a large datapath consisting of multiple cores is resource intensive, with often poor system performance. This paper will introduce a new approach to floating point datapath design for FPGAs, using fused datapath synthesis. The result is a more balanced, high performance implementation, typically saving 50% in both logic resources and latency. Using Stratix (R) 3SE260 devices, 50 GFLOPs double precision and 125 GFLOPs single precision can be realized.
This PhD project aims to tackle the laborious design process of FPGA-based deep neural network (DNN) inference solutions by combining automatic machine learning (AutoML) algorithms with a compiler for custom-tailored ...
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ISBN:
(纸本)9798350341515
This PhD project aims to tackle the laborious design process of FPGA-based deep neural network (DNN) inference solutions by combining automatic machine learning (AutoML) algorithms with a compiler for custom-tailored dataflow accelerator architectures. Manual experiments on a first use case from the RadioML domain suggests great potential for joint optimization of DNN and accelerator, but emphasize the need for empirical quality-of-result (QoR) estimation models, which are the current focus of the project. Future work will entail design space modeling and evaluation of state-of-the-art exploration techniques.
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for fl...
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ISBN:
(纸本)9789090304281
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.
In this paper, we present an ILP formulation to assist designers to identify the architectural design, binding schema and scheduling algorithm while satisfying physical constraints such as available logic resources, c...
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ISBN:
(纸本)9781424419609
In this paper, we present an ILP formulation to assist designers to identify the architectural design, binding schema and scheduling algorithm while satisfying physical constraints such as available logic resources, computation time and memory usage used. Directing the solver to optimise for logic usage, execution time, or other parameters allows ease of exploration of the design space. This case study shows how a proposed ILP formulation solves the design exploration problem in the domain of FPGA-based MPSoC design.
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabricati...
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ISBN:
(纸本)9789090304281
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an fieldprogrammable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. The results show that the bit errors in our PUFs are reduced to less than 1%.
In this research, we introduce FPGA based fuzzy logic controller (FLC). The benefit of using FPGA based FLC compare to software FLC is that the computation time reduction. Using this FLC, we design automated car back ...
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ISBN:
(纸本)9781424403127
In this research, we introduce FPGA based fuzzy logic controller (FLC). The benefit of using FPGA based FLC compare to software FLC is that the computation time reduction. Using this FLC, we design automated car back parallel parking system also with complete FPGA based controller. We build a small-scaled robot car and test on a real environment with VHDL code for wall following and parking. This paper describes the background of fuzzy logic system, the design of fuzzy logic system with FPGA and the experimental results.
""The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such ar...
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ISBN:
(纸本)9781479900046
""The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such arrays are usually referred to as coarse-grained rec""
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