The proceedings contain 10 papers. The topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL...
ISBN:
(纸本)9783800744435
The proceedings contain 10 papers. The topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.
The proceedings contain 9 papers. The topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded softwa...
ISBN:
(纸本)9783800747238
The proceedings contain 9 papers. The topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded software on soft-core MPSoCs through automatic loop transformations;exact mapping of rewritten linear functions to configurable logic;ZUCL: a ZYNQ UltraScale+ framework for OpenCL HLS applications;unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs;HatScheT: a contribution to agile HLS;LeFlow: enabling flexible fpga high-level synthesis of tensorflow deep neural networks;a case study in using OpenCL on FPGAs: creating an open-source accelerator of the AutoDock molecular docking software;and a journey into DSL design using generative programming: FPGA mapping of image border handling through refinement.
The proceedings contain 63 papers. The topics discussed include: compiler discovered dynamic scheduling of irregular code in high-level synthesis;challenges using FPGA clusters for distributed CNN training;HashCache: ...
ISBN:
(纸本)9798350341515
The proceedings contain 63 papers. The topics discussed include: compiler discovered dynamic scheduling of irregular code in high-level synthesis;challenges using FPGA clusters for distributed CNN training;HashCache: high-performance state tracking for resilient FPGA-based packet processing;Co-Visu: a video super-resolution accelerator exploiting codec information reuse;exploring highly quantized neural networks for intrusion detection in automotive CAN;Titan 2.0: enabling open-source CAD evaluation with a modern architecture capture;pipeline balancing for integrated mapping in high performance spatial programmable architecture;FPGA-accelerated causal discovery with conditional independence test prioritization;and FPL demo: a learning-based motion artefact detector for heterogeneous platforms.
The proceedings contain 111 papers. The topics discussed include: an FPGA-based transverse multibunch feedback system for diamond light source;control techniques for coupling a coarse-grain reconfigurable array with a...
ISBN:
(纸本)9780769541792
The proceedings contain 111 papers. The topics discussed include: an FPGA-based transverse multibunch feedback system for diamond light source;control techniques for coupling a coarse-grain reconfigurable array with a generic RISC core;exploiting dynamic reconfiguration for FPGA based network intrusion detection systems;a scalable, high-performance motion estimation application for a weakly-programmable FPGA architecture;efficiently generating FPGA configurations through a stack machine;a reconfigurable system based on a parallel and pipelined solution for regular expression matching;automation framework for large-scale regular expression matching on FPGA;parallel hardware implementation of connected component tree computation;high-performance integer factoring with reconfigurable devices;advanced multithreading architecture with hardware based scheduling;and a reconfigurable computing scheduler optimized for multicore systems.
The proceedings contain 77 papers. The topics discussed include: BunchBloomer: cost-effective bloom filter accelerator for genomics applications;ultra-flow: an ultra-fast and high-quality optical flow accelerator with...
ISBN:
(纸本)9781665473903
The proceedings contain 77 papers. The topics discussed include: BunchBloomer: cost-effective bloom filter accelerator for genomics applications;ultra-flow: an ultra-fast and high-quality optical flow accelerator with deep feature matching on FPGA;virtualization of reconfigurable mixed-criticality systems;tram: an open-source template-based reconfigurable architecture modeling framework;a flexible real-time stereo vision architecture for multiple data streams with runtime configurable parameters;optimized mappings for symmetric range-limited molecular force calculations on FPGAs;the design method of logic circuits based on the voltage-input enhanced scouting logic gates;reducing FPGA memory footprint of stencil codes through automatic extraction of memory patterns;model-based generation of hardware/software architectures for robotics systems;and direct device-to-device physical page migrations in multi-FPGA shared virtual memory systems.
The proceedings contain 64 papers. The topics discussed include: a deep-learning framework for predicting congestion during FPGA placement;lightweight side-channel protection using dynamic clock randomization;executin...
ISBN:
(纸本)9781728199023
The proceedings contain 64 papers. The topics discussed include: a deep-learning framework for predicting congestion during FPGA placement;lightweight side-channel protection using dynamic clock randomization;executing ARMv8 loop traces on reconfigurable accelerator via binary translation framework;precise pointer analysis in high-level synthesis;LFTSM: lightweight and fully testable SEU mitigation system for Xilinx processor-based SoCs;a high throughput MobileNetV2 FPGA implementation based on a flexible architecture for depthwise separable convolution;hardware acceleration of Monte-Carlo sampling for energy efficient robust robot manipulation;and automated design of FPGAs facilitated by cycle-free routing.
The proceedings contain 141 papers. The topics discussed include: efficient and side-channel-secure block cipher implementation with custom instructions on FPGA;data coding functions for software defined radios implem...
ISBN:
(纸本)9781467322560
The proceedings contain 141 papers. The topics discussed include: efficient and side-channel-secure block cipher implementation with custom instructions on FPGA;data coding functions for software defined radios implemented on R3TOS;EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip;SecURe DPR: secure update preventing replay attacks for dynamic partial reconfiguration;using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs;efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources;routing algorithms for FPGAs with sparse intra-cluster routing crossbars;parallel FPGA-based all pairs shortest paths for sparse networks: a human brain connectome case study;a scalable FPGA-based design for fieldprogrammable large-scale ion channel simulations;and scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation.
The proceedings contain 71 papers. The topic discussed include: reducing dynamic power in streaming CNN hardware accelerators by exploiting computational redundancies;Limago: an FPGA-based open-source 100 GbE TCP/IP s...
ISBN:
(纸本)9781728148847
The proceedings contain 71 papers. The topic discussed include: reducing dynamic power in streaming CNN hardware accelerators by exploiting computational redundancies;Limago: an FPGA-based open-source 100 GbE TCP/IP stack;a high-performance CNN processor based on FPGA for MobileNets;measuring long wire leakage with ring oscillators in cloud FPGAs;real-time multi-pedestrian detection in surveillance camera using FPGA;pyramid: machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design;timing-aware routing in the RapidWright framework;and beyond the limits: SHA-3 in just 49 slices.
The proceedings contain 130 papers. The topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital convers...
ISBN:
(纸本)9783000446450
The proceedings contain 130 papers. The topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital conversion;using high-level knowledge to enhance data channels in FPGA streaming systems;hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC;efficient multi-standard cognitive radios on FPGAs;biomedical image processing and reconstruction with dataflow computing on FPGAs;improve defect tolerance in a cluster of a SRAM-based mesh of cluster FPGA using hardware redundancy;efficient implementation of a single-precision floating-point arithmetic unit on FPGA;a fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique;a soft-core processor for finite field arithmetic with a variable word size accelerator;and ultrasmall: the smallest MIPS soft processor.
The proceedings contain 144 papers. The topics discussed include: FPGA: the future platform for transforming, transporting and computing data;increasing the level of abstraction in FPGA-based designs;modeling recursio...
ISBN:
(纸本)9781424419616
The proceedings contain 144 papers. The topics discussed include: FPGA: the future platform for transforming, transporting and computing data;increasing the level of abstraction in FPGA-based designs;modeling recursion data structures for FPGA-based implementation;a portable abstraction layer for hardware threads;fast toggle rate computation for FPGA circuits;on-the-fly attestation of reconfigurable hardware;real-time image super resolution using an FPGA;FPGA family composition and effects of specialized blocks;non-break dynamic defragmentation of reconfigurable devices;scalable high-throughput SRAM-based architecture for IP-lookup using FPGA;mining association rules with systolic trees;loop uprolling and shifting for reconfigurable architectures;FPGA implementation of a flexible decoder for long LDPC codes;and enhancing security of ring oscillator-based TRNG implemented in FPGA.
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