The proceedings contain 107 papers. The topics discussed include: proposal for a vacuum thermal evaporation deposition monitoring system using fuzzy models and ai elements;image classification of roughness using feed ...
ISBN:
(纸本)9798350310634
The proceedings contain 107 papers. The topics discussed include: proposal for a vacuum thermal evaporation deposition monitoring system using fuzzy models and ai elements;image classification of roughness using feed forward artificial neural network;integrated intelligent services accelerator platform;comparative study on the drying of wood chips with different humidities and sizes in a microwave field;considerations in mitigating Kerberos vulnerabilities for active directory;versatile control of an automotive assembly line by using programmablelogic controllers;control system of an autonomous object tracking robot;fitting empirical distributions for vessels behavioral analysis and maritime anomaly detection;hydrogen production and use: an overview of its importance in mitigating climate change and its nexus with renewable and power engineering;integrative therapeutic music-based application for Alzheimer’s disease;quantum fingerprint scrambling algorithm based on chaos theory;integral methods for calculating the magnetic field intensity for a cylindrical permanent magnet;and face-tracking mount display for medical and engineering applications.
Physically Unclonable Functions (PUFs) are used for securing electronic devices across the implementation spectrum ranging from fieldprogrammable Gate Array (FPGA) to system on chips (SoCs). However, existing PUF imp...
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ISBN:
(纸本)9798350339314
Physically Unclonable Functions (PUFs) are used for securing electronic devices across the implementation spectrum ranging from fieldprogrammable Gate Array (FPGA) to system on chips (SoCs). However, existing PUF implementations often suffer from one or more significant deficiencies: (1) significant design overhead;(2) difficulty to configure and integrate based on application-specific requirements;(3) vulnerability to model-building attacks;and (4) spatial locality to a specific region of a chip. These factors limit their application in the authentication of designs used in various applications. In this work, we propose MeLPUF: Memory-in-logic PUF;a low-overhead distributed PUF that leverages the existing logic gates in a design to create cross-coupled inverters (i.e., memory cells), in a logic circuit as an entropy source. It exploits these memory cells' power-up states as the source of entropy to generate device-specific unique fingerprints. A dedicated control signal governs these on-demand memory cells. They can be dispersed across the combinational logic of a design to achieve distributed authentication. They can also be synthesized with a standard logic synthesis tool to meet the target area, power, and performance constraints. We demonstrate the scalability of MeLPUF by aggregating power-up states from multiple memory cells, thus creating PUF signatures or digital identifiers of varying lengths. Our analysis shows the high quality of the PUF in terms of uniqueness, randomness, and robustness while incurring modest overhead.
Commercial hardware-reconfigurable systems-on-chip are highly attractive for mission-critical applications in the space and automotive industries. However, their vulnerability to soft errors is a major concern, and an...
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Emphasizing the critical role of True Random Number Generators (TRNGs) in contemporary cryptographic systems, particularly when integrated with fieldprogrammable Gate Arrays (FPGAs), this work introduces an exception...
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Routing is one of the most time-consuming stages in the FPGA design flow. Parallelization can accelerate the routing process but suffering from load imbalance, further resulting in a low scalahility. In this paper, we...
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ISBN:
(纸本)9781665437592
Routing is one of the most time-consuming stages in the FPGA design flow. Parallelization can accelerate the routing process but suffering from load imbalance, further resulting in a low scalahility. In this paper, we propose a load balance -centric parallel router in a distributed computing environment. First, we explore regular and irregular region partitioning so that routing tasks arc assigned to different cores for static load balance before parallel routing. Second, we explore message propagation and task migration between underloaded and overloaded cores so that load balance can be dynamically maintained at parallel routing runtime. Finally, we demonstrate the effectiveness of the parallel router using large-scale Titan designs. Experimental results show that our parallel router achieves about 17x speedup on average using 32 cores, compared with VTR 8 router.
This paper presents an approach to introduce to the students the concept of the first phase of the compiler-The lexical analysis by developing FPGA based FSMs recognizing different types of lexemes. The aim is to be a...
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Spiking neural networks (SNN) with their 'integrate and fire' (I&F) neurons replace the hardware-intensive multiply-accumulate (MAC) operations in convolutional neural networks (CNN) with accumulate operat...
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ISBN:
(纸本)9781665437592
Spiking neural networks (SNN) with their 'integrate and fire' (I&F) neurons replace the hardware-intensive multiply-accumulate (MAC) operations in convolutional neural networks (CNN) with accumulate operations not only making it easy to implement on FPGAs but also opening up the opportunities for energy-efficient hardware acceleration. In this paper, we propose DeepFire the high-performance RTL IP - for accelerating convolutional SNN inference. The IP exploits various resources available on modern FPGAs, and it outperforms existing SNN implementations by more than 10x in terms of both frame per second (FPS) and performance per watt (FPS/Watt). Our design achieves up to 40.1kFPS and 28.3kFPS on MNIST and CIFAR-10/SVHN datasets with 99.14% and 81.8%/93.1% accuracies respectively. IP was evaluated with 7-series and Ultrascale+ FPGAs from Xilinx achieving Fmax of 375MHz and 500MHz respectively.
In this paper, a programmable current mode Sample Hold (SH) circuit is proposed. The proposed SH is based on the Switched Inverter technique [1], [2]. The circuit employs the conventional CMOS inverter operating as I/...
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Analyzing fetal electrocardiogram (FECG) signals is essential for identifying fetal cardiac disorders early on, although noise interference is still a problem. Conventional signal processing techniques can produce con...
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Deep neural networks are widely used in personalized recommendation systems. Such models involve two major components: the memory-bound embedding layer and the computation-bound fully-connected layers. Existing soluti...
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ISBN:
(纸本)9781665437592
Deep neural networks are widely used in personalized recommendation systems. Such models involve two major components: the memory-bound embedding layer and the computation-bound fully-connected layers. Existing solutions are either slow on both stages or only optimize one of them. To implement recommendation inference efficiently in the context of a real deployment, we design and implement an FPGA cluster optimizing the performance of both stages. To remove the memory bottleneck, we take advantage of the High-Bandwidth Memory (HBM) available on the latest FPGAs for highly concurrent embedding table lookups. To match the required DNN computation throughput, we partition the workload across multiple FPGAs interconnected via a 100 Gbps TCP/IP network. Compared to an optimized CPU baseline (16 vCPU, AVX2-enabled) and a one-node FPGA implementation, our system (four-node version) achieves 28.95x and 7.68x speedup in terms of throughput respectively. The proposed system also guarantees a latency of tens of microseconds per single inference, significantly better than CPU and GPU-based systems which take at least milliseconds.
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