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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"
16726 条 记 录,以下是221-230 订阅
排序:
Variable-Latency Signed Addition on FPGAs  25
Variable-Latency Signed Addition on FPGAs
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25th international conference on field programmable logic and applications
作者: Cilardo, Alessandro Univ Naples Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy
Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands hav... 详细信息
来源: 评论
SECURE FPGA TECHNOLOGIES AND TECHNIQUES
SECURE FPGA TECHNOLOGIES AND TECHNIQUES
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19th international conference on field programmable logic and applications
作者: Braeken, An Kubera, Serge Trouillez, Frederik Touhafi, Abdellah Mentens, Nele Vliegen, Jo Erasmushogesch Brussel Dept IWT Nijverheidskaai 170 B-1070 Anderlecht Belgium Vrije Univ Brussel B-1050 Brussels Belgium Katholieke Univ Leuven ESAD SCD CISUC Leuven Belgium Katholieke Hogesch Limburg IWT ACRO Dipenbeek Belgium
This survey paper proposes an overview of contemporary FPGA-related technologies and techniques that can be used for data and system security. As such we will give an overview of the currently available features in co... 详细信息
来源: 评论
Demonstration of Flow-in-Cloud: A multi-FPGA system  29
Demonstration of Flow-in-Cloud: A multi-FPGA system
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29th international conference on field-programmable logic and applications (FPL)
作者: Hironaka, Kazuei Iizuka, Kensuke Ben Ahmed, Akram Ullah, M. M. Imdad Yamauchi, Yugo Sun, Yuxi Yamakura, Miho Hiruma, Aoi Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan
Flow-in-Cloud(FiC) is an acceleration platform designed to make a virtual monolithic large FPGA image from a number of mid-range economical FPGAs. We will show the live demonstration of the acceleration example of FiC... 详细信息
来源: 评论
CHIMPS: A C-LEVEL COMPILATION FLOW FOR HYBRID CPU-FPGA ARCHITECTURES
CHIMPS: A C-LEVEL COMPILATION FLOW FOR HYBRID CPU-FPGA ARCHI...
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18th international conference on field programmable and logic applications
作者: Putnam, Andrew Bennett, Dave Dellinger, Eric Mason, Jeff Sundararajan, Prasanna Eggers, Susan Xilinx Res Labs Longmont CO 80503 USA
This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPS's goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANS... 详细信息
来源: 评论
FISH: Linux System Calls for FPGA Accelerators  27
FISH: Linux System Calls for FPGA Accelerators
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27th international conference on field programmable logic and applications (FPL)
作者: Nam, Kevin Fort, Blair Brown, Stephen Univ Toronto ECE Dept Toronto ON Canada
This paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. A special FISH Linux kernel module runnin... 详细信息
来源: 评论
A congestion driven placement algorithm for FPGA synthesis
A congestion driven placement algorithm for FPGA synthesis
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16th international conference on field programmable logic and applications
作者: Zhuo, Yue Li, Hao Mohanty, Saraju P. Univ N Texas Dept Comp Sci & Engn POB 311366 Denton TX 76203 USA
We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion meth... 详细信息
来源: 评论
INCREASING STABILITY AND DISTINGUISHABILITY OF THE DIGITAL FINGERPRINT IN FPGAS THROUGH INPUT WORD ANALYSIS
INCREASING STABILITY AND DISTINGUISHABILITY OF THE DIGITAL F...
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19th international conference on field programmable logic and applications
作者: Patel, Hiren Kim, Yong McDonald, J. Todd Starman, LaVern USAF AF Res Lab 1940 Allbrook Dr Wright Patterson AFB OH 45433 USA Air Force Inst Technol Wright Patterson AFB OH 45433 USA
field programmable Gate Arrays (FPGAs) have become increasingly popular in circuit development due to their rapid development times and low costs. With their increased use, the need to protect their Intellectual Prope... 详细信息
来源: 评论
FPGA based imaging particle detector trigger system
FPGA based imaging particle detector trigger system
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16th international conference on field programmable logic and applications
作者: Martinez, Gustavo Marin, Jesus Willmott, Carlos Elect & Sensores Ciemat Avda Complutense 22 Madrid 28040 Spain
An FPGA based trigger system for an imaging particle detector has been designed and produced. The main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of ... 详细信息
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A high speed, low memory FPGA based LDPC decoder architecture for quasi-cyclic LDPC codes
A high speed, low memory FPGA based LDPC decoder architectur...
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16th international conference on field programmable logic and applications
作者: Saunders, Paul Fagan, Anthony D. Univ Coll Dublin DSP Res Lab Sch Elect Elect & Mech Engn Dublin 2 Ireland
We propose a novel, high speed, low memory fully programable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we ar... 详细信息
来源: 评论
Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems  27
Application-Specific Soft-Core Vector Processor for Advanced...
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27th international conference on field programmable logic and applications (FPL)
作者: Nolting, Stephan Giesemann, Florian Hartig, Julian Schmider, Achim Paya-Vaya, Guillermo Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany
Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. The massive computational demands under hard real-time and energy constraints c... 详细信息
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