""We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recogn...
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ISBN:
(纸本)9781479900046
""We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recognition.""
The widely accepted block-matching technique, which is required to identify motion vectors, fails in cases in which texture is not existent. In [1], we proposed a hardware-oriented cellular-automaton algorithm that ge...
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ISBN:
(纸本)9789090304281
The widely accepted block-matching technique, which is required to identify motion vectors, fails in cases in which texture is not existent. In [1], we proposed a hardware-oriented cellular-automaton algorithm that generates spatial patterns on textureless objects and backgrounds, aiming at motion-vector estimation of textureless moving objects. This demonstration presents a field-programmable gate array (FPGA) system that supports real-time processing. This system provides motion-vectors in moving textureless objects and enables enhanced processing of motion vector classification.
A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly uti...
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ISBN:
(纸本)9781424410590
A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation;an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature;100 frames per second;can be achieved.
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-...
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ISBN:
(纸本)9781424438914
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. This paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. This paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.
Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed-and now routed - solution that can be programmed onto the Xilinx commer...
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ISBN:
(纸本)9781467381239
Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed-and now routed - solution that can be programmed onto the Xilinx commercial FPGA architecture. Secondly, we apply this updated tool to measure the gap between academic and industrial FPGA tools by examining the quality of results at each of the three main compilation stages: synthesis, packing & placement, routing. Our findings indicate that the delay gap (according to Xilinx static timing analysis) for academic tools breaks down into a 31% degradation with synthesis, 10% with packing & placement, and 15% with routing. This leads us to believe that opportunities for improvement exist not only within VPR, but also in the front-end tools that lie upstream.
This paper develops a formal model of process migration that describes pro.-rams, processes, and the migration of those processes within a migration realm. A migration realm is a group of processors modeled as finite ...
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ISBN:
(纸本)9781424410590
This paper develops a formal model of process migration that describes pro.-rams, processes, and the migration of those processes within a migration realm. A migration realm is a group of processors modeled as finite state machines. The model is motivated by a migration application between software and fieldprogrammable Gate Array (FPGA) hardware, and the theorems of the model guide the use of FPGA resources while guaranteeing complete and correct execution of a process. By defining different types of migration realms this paper also develops a migration realm taxonomy.
In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability...
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ISBN:
(纸本)9789090304281
In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean models does not scale for such state-of-the-art complex Boolean models. We propose fieldprogrammable Gate Arrays (FPGAs) for emulation of Boolean models, exploiting the highly parallel nature of FPGAs. Our emulation framework consists of converting a Boolean model to Verilog, connecting it to an execution core, which runs on an FPGA coherently attached to a POWER8 processor. We report an order of magnitude speed up over a multi-threaded software simulation tool running on the same processor.
A method is described for enumerating the frequencies of DNA subsequences on a system comprising a host computer and a fieldprogrammable gate array (FPGA) board with one FPGA. Frequencies of subsequences with lengths...
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ISBN:
(纸本)9781424410590
A method is described for enumerating the frequencies of DNA subsequences on a system comprising a host computer and a fieldprogrammable gate array (FPGA) board with one FPGA. Frequencies of subsequences with lengths of up to K-0 K-1 K-2 (24 in the current implementation) are enumerated in three phases. In these three phases, subsequences with lengths of up to K-0, K (0) K-1, and K-0 K-1 K-2, respectively, are enumerated;these three phases are executed simultaneously on a pipelined circuit, resulting in high performance. The enumeration of frequent subsequences in databases, which are becoming larger and larger, will enable subsequences that are unique and/or repeatedly used in many parts of the sequences to be found.
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA...
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ISBN:
(纸本)9781424410590
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. fieldprogrammable gate arrays (FPGAs) are in the spotlight these days: not only due to ...
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ISBN:
(纸本)9789090304281
As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. fieldprogrammable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. The latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first-the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. This paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration.
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