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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"
16761 条 记 录,以下是321-330 订阅
排序:
FPGA-based All-digital Software Defined Radio System Demonstration  25
FPGA-based All-digital Software Defined Radio System Demonst...
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25th international conference on field programmable logic and applications
作者: Cordeiro, Rui F. Prata, Andre Oliveira, Arnaldo S. R. Carvalho, Nuno Borges Vieira, Jose N. Univ Aveiro DETI Inst Telecomunicacoes Aveiro Portugal
All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques an... 详细信息
来源: 评论
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
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18th international conference on field programmable and logic applications
作者: Saegusa, Takashi Maruyama, Tsutomu Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058573 Japan
In image processing, FPGAs have shown very high performance in spite of their low operational frequency. This high performance comes from (1) high parallelism in applications in image processing, (2) high ratio of 8 b... 详细信息
来源: 评论
FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs  32
FPL Demo: SERVE: Agile Hardware Development Platform with Cl...
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32nd international conference on field-programmable logic and applications (FPL)
作者: Wang, Zelin Zhang, Ke Chang, Yisong Yin, Yanlong Chen, Yuxiao Zhao, Ran Wang, Songyue Chen, Mingyu Bao, Yungang Chinese Acad Sci State Key Lab Processor ICT Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China
We introduce SERVE, a cloud platform for agile hardware software co-design, with cloud IDE and cloud FPGAs integrated. SERVE enables users to focus on logic designs, without facing the hassle of setting up FPGA tools ... 详细信息
来源: 评论
PERFORMANCE EVALUATION OF SPARSE MATRIX-MATRIX MULTIPLICATION
PERFORMANCE EVALUATION OF SPARSE MATRIX-MATRIX MULTIPLICATIO...
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23rd international conference on field programmable logic and applications (FPL)
作者: Jain-Mendon, Shweta Sass, Ron Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA
The conventional matrix multiplication algorithms that are suitable for dense matrices do not perform well on the corresponding Sparse Matrix-Matrix Multiplication (SMMM) operation. In particular, they do not utilize ... 详细信息
来源: 评论
Hardware Acceleration of a Software-based VPN  26
Hardware Acceleration of a Software-based VPN
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26th international conference on field-programmable logic and applications (FPL)
作者: Turan, Furkan de Clercq, Ruan Maene, Pieter Reparaz, Oscar Verbauwhede, Ingrid Katholieke Univ Leuven COSIC Dept Elect Engn ESAT Leuven Belgium IMinds Ghent Belgium
A Virtual Private Network (VPN) encrypts and decrypts the private traffic it tunnels over a public network. Maximizing the available bandwidth is an important requirement for network applications, but the cryptographi... 详细信息
来源: 评论
A Partial Reconfiguration Controller for Altera Stratix V FPGAs  26
A Partial Reconfiguration Controller for Altera Stratix V FP...
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26th international conference on field-programmable logic and applications (FPL)
作者: Xiao, Zhenzhong Koch, Dirk Lujan, Mikel Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England
With the introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigura... 详细信息
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GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES
GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES
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19th international conference on field programmable logic and applications
作者: de Dinechin, Florent Klein, Cristian Pasca, Bogdan Univ Lyon LIP CNRS INRIA ENSLyon UCBL Ecole Normale Super Lyon F-69364 Lyon France
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application ... 详细信息
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Accelerating Traditional Object Detection Methods on Sophisticated Embedded Systems  4th
Accelerating Traditional Object Detection Methods on Sophis...
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4th international conference on Intelligent Systems and Pattern Recognition, ISPR 2024
作者: Sehairi, Kamal Bouhafs, Abdelkader Boucherit, Ibtissam Mama Bouwmans, Thierry Chouireb, Fatima Department of Physics Laboratory of Applied Sciences and Didactics École Normale Supérieure de Laghouat Laghouat Algeria Department of Electronics Telecommunication Signals and Systems Laboratory University Amar Telidji of Laghouat Laghouat Algeria Department of Computer Science Lab. Mathématiques Image et Applications Université de La Rochelle La Rochelle France
Identifying and locating objects in images and videos, including elements like traffic signs, vehicles, buildings, and people, constitutes a fundamental and demanding task in computer vision, known as object detection... 详细信息
来源: 评论
EXPLOITING FAST CARRY-CHAINS OF FPGAS FOR DESIGNING COMPRESSOR TREES
EXPLOITING FAST CARRY-CHAINS OF FPGAS FOR DESIGNING COMPRESS...
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19th international conference on field programmable logic and applications
作者: Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conv... 详细信息
来源: 评论
TIMING DRIVEN RTL-TO-RTL PARTITIONER FOR MULTI-FPGA SYSTEMS
TIMING DRIVEN RTL-TO-RTL PARTITIONER FOR MULTI-FPGA SYSTEMS
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23rd international conference on field programmable logic and applications (FPL)
作者: Strauch, Tobias EDAptix R&D D-80538 Munich Germany
This paper discusses a novel RTL to RTL partitioner flow to better cope with the challenges of modern rapid system prototyping on Multi-FPGA sytems. The proposed system partitioner flow is timing driven to evaluate th... 详细信息
来源: 评论