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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16720 条记录，以下是321-330 订阅

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A Hardware Efficient Real-time Video processing on FPGA with OV 7670 camera interface and VGA 6

A Hardware Efficient Real-time Video processing on FPGA with...

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6th international conference on Electronics, Communication and Aerospace Technology, ICECA 2022

作者： Navaneethan, S. Thanusha, Chenimineni Varshini, M. Amirdha Anil, Ankireddygari Saveetha Engineering College Dept. of Ece Chennai India

ISBN: (纸本)9781665482714

The aim of this work is to develop a video processing system with efficient hardware resource using a field programmable gate array (FPGA). The FPGA board contains several resources that may be implemented on both hardware and software platforms. Real-time video processing necessitates high-consuming logic resources, and fpga is an excellent choice for video processing applications. In this work, Omni vision (OV) 7670 and Video graphics array (VGA) interfaces with FPGA for video processing system. The tools utilized here are Xilinx Vivado and Verilog HDL to develop the system. The proposed video processing system implemented in Spartan 6 &Artix -7 FPGA which provides 530 slice registers. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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Demonstration system of reconfigurable multi-valued logic electronic processor 2

Demonstration system of reconfigurable multi-valued logic el...

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2nd international conference on Electronic Information Technology, EIT 2023

作者： Lu, Yao Wang, Hongjian Huang, Jun Zhou, Xinyu Wu, Youdong College of Computer Science and Technology Donghua University Shanghai China Institute of Advanced Technology University of Science and Technology of China Anhui China

ISBN: (数字)9781510666627

ISBN: (纸本)9781510666610

The reconfigurable multi-valued logic processor consists of a large number of processor units that can be grouped and reconfigured at runtime, enabling it to implement a wide variety of logic operators and many-bit parallel adders. In this study, we design and implement a demonstration system of an FPGA-based reconfigurable multi-valued logic processor using the AX7020 development board. To demonstrate the system's capabilities, we develop a demonstration program based on embedded Linux and Qt, which includes a graphical user interface for a 1000-trit reconfigurable ternary logic processor, a 32-quit reconfigurable quaternary logic processor and a 64-bit MSD adder. The program runs on the ARM Cortex-A9 processor on the PS side of the development board, with human-machine interaction achieved through the AN970 7-inch LCD touch screen external to the PL side of the development board. We verify the reliability of the reconfigurable multi-valued logic electronic processor's hardware functions in the demonstration system through various means, including software simulation checking, automatic random tests and manual tests on the demonstration system. The results show that the demonstration system can let users experience the characteristics of reconfigurable multi-valued logic electronic processor, such as processor units grouping and reconfiguration, ternary/quaternary logic operations and MSD addition operations, through the touch screen in a user-friendly way. © 2023 SPIE.

关键词： field programmable gate arrays (FPGA)

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Enhancing Urban Water Distribution: The Role of Automated Systems and PLC applications

Enhancing Urban Water Distribution: The Role of Automated Sy...

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2024 IEEE international conference on Modeling, Simulation and Intelligent Computing, MoSICom 2024

作者： Ashique, Abdul Azeez Rebello, Ashton Subramanian, Ganesan Chandrasekar, Naveen Manipal Academy of Higher Education Dept. of Mechatronics Engineering Dubai United Arab Emirates Dubai. Manipal Academy of Higher Education Dept of Computer Studies Symbiosis International University Dubai United Arab Emirates

ISBN: (纸本)9798331533311

Due to the increase in population accompanied by the expansive growth of urban residential areas, the demand for efficient and reliable water distribution systems has increased rapidly. And as urbanisation increases day by day this demand for water is equal to the need for sustainable water management and distribution systems. Thus, it becomes an utmost necessity for the implementation of proper controlling and monitoring mechanisms to prevent wastage of water and also attempts of water theft. As a solution to these challenges, many advanced technologies have been identified all over the world to ensure effective distribution of water to reach every household especially in urban areas. Therefore, my paper estimates and understands the current state of automated water distribution systems with a prime focus on monitoring performance and control through PLC (programmable logic controller) applications. In the initial areas of this paper, it focuses on the basic concept of automatic water distribution that has been implemented in the current scenario in urban areas. This study includes thorough research on the details of the system, how it is operated, its principles, and intended functions. The next stage of research will be focussed on a comparative analysis of various technologies that have been studied and implemented in the field of automated water distribution. This paper shows key innovations, challenges and future goals in the realm of automated water distribution. It also shows the possibility for the integration of PLC systems, discussing how efficiently these systems contribute to the optimization of the water distribution process. Thus, proving PLC systems plays a crucial role in improving the overall performance and sustainability of water distribution systems by monitoring real-time data. © 2024 IEEE.

关键词： Water distribution systems

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Unipolar and Bipolar Mathematical Inference of Weight Adjustment Mode of Single Layer Perceptron on and logic Gate 3

Unipolar and Bipolar Mathematical Inference of Weight Adjust...

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3rd international conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, ICAECT 2023

作者： Devi, M. Shyamala Goni, S. Tasneem, P. Vintha, Karthikeyani Kumar, Dubba Sai Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology Computer Science & Engineering Tamilnadu Chennai India

ISBN: (纸本)9781665494007

In order to ensure that electrical terminals only 'switch on' after the proper logic process has been applied, logic gates are employed to make judgments. Each logic gate has a name that explains how various inputs will affect the potential outcomes. To perform logical functions on one or more binary sequence of inputs and produce a single digital output, logic gates are utilized. Embedded systems, microcontrollers, electrical and electronics circuit boards, and programmable logic applications generally make use of logic gates. When the sensor receives no information, it generates low Output impedance for logic 0. It has been determined that using logic gates to create an edge avoider robotics that lowers project budget and speeds up the robot. With the growth of technology, the neural network could also be used for implementing the logic gate using Single Layer Perceptron neural network often termed as Linear Threshold Gate. This paper attempt to analyze the mathematical inference on the number of execution steps for the weight adjustment in the activation function of AND logic gate. This inference carried out by varying the input of Single layer Perceptron Neural Network in the form of unipolar and bipolar input. The activation function weight adjustment had carried out using batch and sequential mode of execution. Mathematical implementation of AND logic gate exhibits that Bipolar sequential and Bipolar batch mode weight adjustment had less number of execution steps reaching 100% accuracy by matching the desired and predicted output when compared to the unipolar. The detailed execution steps are produced herewith for the validation of outcome. © 2023 IEEE.

关键词： Network layers

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Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision

Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Graine...

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international conference on field programmable logic and applications

作者： Xilai Dai Yuzong Chen Mohamed S. Abdelfattah Department of Electrical and Computer Engineering Cornell University

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

FPGAs offer a flexible platform for accelerating deep neural network (DNN) inference, particularly for non-uniform workloads featuring fine-grained unstructured sparsity and mixed arithmetic precision. To leverage these redundancies, an emerging approach involves partially or fully unrolling computations for each DNN layer. That way, parameter-level and bit-level ineffectual operations can be completely skipped, thus saving the associated area and power. Regardless, unrolled implementations scale poorly and limit the size of a DNN that can be unrolled on an FPGA. This motivates the investigation of new reconfigurable architectures to improve the efficiency of unrolled DNNs, while taking advantage of sparsity and mixed precision. To enable this, we present Kratos: a focused FPGA benchmark of unrolled DNN primitives with varying levels of sparsity and different arithmetic precisions. Our analysis reveals that unrolled DNNs can operate at very high frequencies, reaching the maximum frequency limit of an Arria 10 device. Additionally, we found that substantial area reductions can be achieved through fine-grained sparsity and low bit-width. We build on those results to tailor the FPGA fabric for unrolled DNNs through an architectural case study demonstrating $\sim 2 \times$ area reduction when using smaller LUT sizes within current FPGAs. This paves the way for further exploration of new programmable architectures that are purpose-built for sparse and low-precision unrolled DNNs. Our source code and benchmark are available on ***/abdelfattah-lab/Kratos-benchmark.

关键词： Source coding Redundancy Artificial neural networks Benchmark testing Table lookup Reconfigurable architectures logic High frequency field programmable gate arrays Arithmetic

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JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs

JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs

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international conference on field programmable logic and applications

作者： Tobias Hahn Stefan Wildermann Jürgen Teich Hardware/Software Co-Design Friedrich-Alexander-Universität Erlangen-Närnberg FAU Germany

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Big Data applications frequently involve the processing of data streams encoded in semi-structured data formats such as JSON. A major challenge here is that the parsing of such data formats is usually highly complex. Accelerating JSON parsing on FPGAs has therefore become a focus of recent research. However, as JSON data is highly sparse, compression is frequently applied before writing records to storage or transmitting them over the network. Consequently, the data must be decompressed before parsing it into a suitable format for further *** existing work has addressed decompression and parsing of semi-structured data separately, we propose a co-design for JSON decompression/parsing. This co-design includes a compression scheme tailored specifically for JSON, along with an FPGA parser architecture capable of operating directly on compressed input data. Additionally, our design adopts a lazy decompression approach to only decompress projected attributes, thereby significantly reducing the workload on the decompressor. Our experimental evaluation shows that this co-design exploiting several synergies results in higher resource efficiency compared to existing approaches for JSON parsing on FPGAs, while also enabling the decompression of data. For high compression factors, we observe a 1.8 x increase in parsed JSON tuples per second and LUT compared to the most efficient related approach. Moreover, our presented compression scheme offers higher compression factors for JSON data than related work while providing similar performance.

关键词： Codes Symbols Writing Throughput Table lookup logic Data mining field programmable gate arrays Streams Periodic structures

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Research on Testing Technology of Embedded Processor Cache Controller in programmable SoC 3

Research on Testing Technology of Embedded Processor Cache C...

引用

3rd IEEE international conference on Information Technology, Big Data and Artificial Intelligence, ICIBA 2023

作者： Song, Xingzuo Li, Xuewu Chen, Lei Sun, Huabo Zhang, Fan Beijing Microelectronics Technology Institute Beijing China

ISBN: (纸本)9781665490788

With the progress of Integrated Circuit technology and the multiple needs of human for scalar and reconfigurable operations in intelligent electronic system, a new chip architecture combining traditional FPGA and embedded processor appears, namely programmable SoC. programmable SoC products have been widely used in mission and safety-critical applications, but production defects in hardware and time-related defects in the working process often lead to system misbehavior, which leads to disastrous consequences. Therefore, in view of the long-term reliability application requirements of programmable SoC products, it is necessary to carry out relevant research on its in-field test technology. In this paper, we will use the Software-Based Self Test (SBST) method to explore and implement the function of data cache controller for Zynq-7000 series programmable SoC embedded processors (Enable\Disable, Invalidate, Clean) test technology research. By making full use of the fully programmable features of hardware and software resources in Zynq-7000, we have respectively realized the test generation technology based on PS and the test observation technology based on PL, and designed the prototype test system. Finally, the experimental results show that the prototype test system meets our expectations and can realize the in-field test of the cache controller of the embedded processor in the Zynq-7000 series programmable SoC. At the end of this paper, we summarize the work done and look forward to the future research direction. © 2023 IEEE.

关键词： System-on-chip

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TRUSTED VIRTUALIZATION-BASED programmable logic CONTROLLER RESILIENCE USING A BACKFIT APPROACH 16th

TRUSTED VIRTUALIZATION-BASED PROGRAMMABLE LOGIC CONTROLLER R...

引用

16th international conference on Critical Infrastructure Protection

作者： Cervini, James Muller, Daniel Beall, Alexander Maurio, Joseph Rubin, Aviel Watkins, Lanier Johns Hopkins Univ Baltimore MD 21218 USA Johns Hopkins Univ Appl Phys Lab Laurel MD USA Johns Hopkins Univ Appl Phys Lab Crit Infrastruct Protect Grp Laurel MD USA Johns Hopkins Univ Comp Sci Baltimore MD USA Johns Hopkins Univ Informat Secur Inst Baltimore MD USA

ISBN: (纸本)9783031201394;9783031201370;9783031201363

Industrial control systems perform vital cyber-physical functions in critical infrastructure assets. programmable logic controllers, which are prominently found in industrial control environments, execute the operational control logic of cyber-physical systems. Due to the continued escalation of cyber attacks targeting industrial control systems and programmable logic controllers, strengthening the trust and resilience of these systems is paramount. This chapter proposes an approach that leverages virtualization, cryptographic attestation, software-defined networking, security orchestration and a proprietary programmable logic controller runtime application to advance programmable logic controller trust and resilience while facilitating integration in deployed systems. A proof-of-concept capability demonstrated on a physical industrial control system testbed validates the approach. The experimental results confirm that the approach is viable for industrial control applications.

关键词： Industrial control systems virtualization security

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An Improved Method for High Speed DUC in Broadband Transmitters 7

An Improved Method for High Speed DUC in Broadband Transmitt...

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7th international conference on Electronic Information Technology and Computer Engineering (EITCE)

作者： Zhou, Xinxing Wen, Fei Yan, Ming CSSC Res Inst 722 Wuhan 430205 Hubei Peoples R China

ISBN: (纸本)9798400708305

In the modern broadband transmitters, the sampling rate of DAC is required to be higher and higher, the bandwidth of the transmitted signal, meanwhile, is required to be wider and wider. The traditional method of the digital up conversion (DUC) is unable to meet the demand for the broadband transmission because of the limitation of the clock frequency of the field programmable gate array (FPGA). For broadband transmission applications, an improved method of high speed DUC is proposed. The interpolation filtering and direct digital synthesis (DDS) are optimized. Firstly, the mathematical model of high speed DUC is derived, and the structure of the traditional DUC is improved. The efficient and flexible structures of the interpolation filtering and DDS are designed. Secondly, the calculation method of multichannel coefficients of the interpolation filter is given. The calculation method of multichannel phase parameters of parallel DDS is also given. The hardware implementation shows that the proposed method has correct function, and can be applied to engineering conveniently. The data rate of the digital signal at intermediate frequency (IF) output from the hardware can reach 960MSps. The proposed method can realize interpolations with different multiples, and can also generate high speed local oscillator signals with different rates. It can meet the requirements of transmitting wide band and high rate signals in the modern broadband transmitters.

关键词： Digital up conversion High rate Poly phase filtering field programmable gate array

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Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification

Chimera: A co-simulation framework combining with gem5 and F...

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international conference on field programmable logic and applications

作者： Chao Fu Zengshi Wang Jun Han School of Microelectronics Fudan University China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

To accommodate the requirements of increasingly diverse applications, the scale of System-on-Chip (SoC) has extended beyond single-chip, evolving towards chiplets. This expansion is accompanied by a significant increase in the number of functional IPs. Each new IP undergoes a lengthy development process to meet expected performance and ensure compatibility with existing SoCs. The conventional development process is generally divided into several distinct stages, including architecture exploration, RTL development, standalone testing, and integration verification. As IP complexity escalates and coupling with the software stack becomes intricate, the standalone testing phase fails to guarantee complete IP functionality. This deficiency leads to extended development periods and necessitates numerous iterative design revisions during the integration verification phase, hindering the efficiency of IP integration into SoC. In this paper, we introduce Chimera, the first co-simulation framework that combines ESL simulators and the FPGA platform. The framework streamlines the conventional development process, providing a direct approach to architecture exploration and integration verification of a Register-Transfer Level (RTL) IP within an SoC running on the gem 5 simulator. We propose three optimizations including an optimistic synchronization mechanism, batch processing, and dataflow merging to enhance the efficiency of Chimera. Our experimental results demonstrate that Chimera can sustain co-simulation speeds comparable to the speed of the standalone gem5 simulator within typical system configurations. Furthermore, Chimera outperforms the state-of-the-art co-simulation framework, achieving up to a $20 \times$ performance improvement.

关键词： Merging Computer architecture Software System-on-chip IP networks Synchronization logic field programmable gate arrays Optimization Testing

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