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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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A fast measuring device for impedance spectrum of lithium-ion battery based on FPGA 17

A fast measuring device for impedance spectrum of lithium-io...

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17th conference on Industrial Electronics and applications (ICIEA)

作者： Wang, Bo Lyu, Chao Liu, Tong Zhao, Di Wang, Lixin Harbin Inst Technol Sch Elect Engn & Automat Harbin Peoples R China Harbin Inst Technol Shenzhen Sch Mech Engn & Automat Shenzhen Peoples R China

ISBN: (纸本)9781665409841

Lithium-ion battery quickly developed into a new generation of energy because of its advantages of small selfdischarge, large energy density, good safety and memory-memory *** impedance spectroscopy (EIS) measurements are widely used in the performance evaluation of lithium-ion batteries. At present, the traditional AC impedance spectrum test instrument uses sweeps, which has disadvantages such as long test time and expensive price. This design uses the field programmable gate array (FPGA) as the controller drive peripheral module. Based on the fast Fourier transform (FFT) measurement method, the upper computer software is developed for data processing and impedance spectrum mapping. The design is mainly divided into FPGA control logic and upper computer software. FPGA control logic adopts modular design. The top level is divided into data analysis module, control module, signal occurrence module, analog to digital conversion module, FIFO cache module and USB communication module to realize superimposed sine signal occurrence, data acquisition and communication with upper computer. The upper computer software design is based on the Visual Studio development environment, developed using C # and Windows Form, realizing the function of data sending and receiving, data processing, and impedance spectrum mapping. This design verified the reproducibility of the system using multiple measurements, yielding the standard deviation of multiple measurements. The accuracy of the system was verified using a comparison with the acquisition card-based measurement device. The results show that this system can be used as a tool to measure the impedance spectrum of lithium-ion batteries.

关键词： Lithium-ion battery Electrochemical impedance spectrum field programmable gate array Fast Fourier transform

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Q2logic: A Coarse-Grained FPGA Overlay targeting Schrödinger Quantum Circuit Simulations

Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinge...

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2023 IEEE international Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023

作者： Podobas, Artur KTH Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden

ISBN: (纸本)9798350311990

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore's law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture- architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2logic. Q2logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on field-programmable Gate Arrays (FPGAs), but specialized towards quantum simulations. We described how Q2logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2logic can be up-to 7x faster. © 2023 IEEE.

关键词： Circuit simulation

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CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop Using Transmission Gate logic for Low Power VLSI applications

CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop U...

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2025 international conference on Multi-Agent Systems for Collaborative Intelligence, ICMSCI 2025

作者： Nagarajan, P. Lalith Kumar, S. Hariharan, M. Nitheesh, S. Krishnan, Rahul Bhairavi, R. Srm Institute of Science and Technology Department of Ece Tamilnadu Chennai India

ISBN: (纸本)9798331509828

The rapid evolution of low-power applications in VLSI design calls for innovative transistor technologies that are capable of meeting stringent energy efficiency requirements. Carbon Nanotube field-Effect Transistors (CNTFETs) offer significant advantages over conventional MOSFETs, particularly in nanoscale, low-power, and high-performance circuits. This paper presents a comparative study of two Flip-Flop circuits aimed at power-efficient digital design. The first circuit, an existing design Pass Transistor logic based Implicit Pulsed - Dual Edge Triggered Flip-Flop (PTIP-DETFF) [1] which was originally implemented using MOSFET technology, has been converted into CNTFET technology to facilitate direct performance comparison. The second circuit is a novel CNTFET-based design that employs Pulse Implied Binary Edge Activated Flip-Flop (PI-BEAFF) using Transmission Gate logic, resulting in further optimization of power and delay characteristics. Simulation results reveal that the proposed CNTFET-based flip-flop, designed using 32nm technology, achieves a power reduction of approximately 99.73% and a delay reduction of 41.53%, with an average power of 5.52654 nW and delay of 8.58667 ps, compared to 2.0290 μ W and 14.685 ps in the existing circuit. This analysis considers critical metrics, including Power-Delay-Product (PDP), Energy-Delay-Product (EDP), Power-Energy-Product (PEP), transistor count, and the number of clocked transistors. The results underscore the potential of CNTFET technology in realizing low-power, high-speed digital circuits, highlighting its applicability for future energy-efficient VLSI systems. © 2025 IEEE.

关键词： Flip flop circuits

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A data backup optimization mechanism for the virtual FPGA cluster 6

A data backup optimization mechanism for the virtual FPGA cl...

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6th international conference on Information Science, Electrical, and Automation Engineering, ISEAE 2024

作者： Liu, Wei Fang, Yu Zhang, Jingdong Shen, Yanmei Zhao, Kun Su, Dongdong Architecture Research Department Guangdong Inspur Intelligent Computing Technology Co. Ltd. Guangzhou China

ISBN: (纸本)9781510682924

As a heterogeneous computing architecture, FPGA accelerators are widely used for AI and other fields. Compared with traditional CPU clusters, the architecture of the virtual FPGA cluster is relatively simple, and thus lacks the design of relevant mechanisms for data backup. In our work, a data backup optimization mechanism for the virtual FPGA cluster is proposed to select local sub-kernels and remote sub-kernels of other FPGA accelerators as data backups. During the selection of remote sub-kernel backups, the data transmission delay between the sub-kernel under evaluation and the sub-kernel to be backed up, the statistical probability of the historical errors of the sub-kernel under evaluation, and the internal environment influence factors in its FPGA accelerator are fully considered. The simulation results demonstrate that the proposed data backup optimization mechanism has shown good data disaster recovery performance. © 2024 SPIE.

关键词： field programmable gate arrays logic Data backup Data transmission Computer architecture Power consumption

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Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

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2025 IEEE international conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Wu, Yun McAllister, John School of Electrical Electronic and Computer Engineering Queen's University Belfast United Kingdom

ISBN: (纸本)9798350368741

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×. © 2025 IEEE.

关键词： Approximate Computing Compressive Sensing Convex Optimization Depth Reconstruction field-programmable Gate Array

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Speed Records in Network Flow Measurement on FPGA

Speed Records in Network Flow Measurement on FPGA

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31st international conference on field-programmable logic and applications (FPL)

作者： Sateesan, Arish Vliegen, Jo Scherrer, Simon Hsiao, Hsu-Chun Perrig, Adrian Mentens, Nele Katholieke Univ Leuven ESAT IMEC COSIC ES&S Leuven Belgium Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland Natl Taiwan Univ Taipei Taiwan Leiden Univ LIACS Leiden Netherlands

ISBN: (纸本)9781665437592

Network traffic measurement keeps track of the amount of traffic sent by each flow in the network. It is a core functionality in applications such as traffic engineering and network intrusion detection. In high-speed networks, it is impossible to keep an exact count of the flow traffic, due to limitations with respect to memory and computational speed. Therefore, probabilistic data structures, such as sketches, are used. This paper proposes Approximate Count-MM sketch or A-CM sketch, a novel variant of the Count-MM sketch algorithm that uses less memory and has a higher throughput compared to other FPGA-based sketch implementations. A-CM sketch relies on optimizations at two levels: (1) it uses approximate counters and the newly proposed Hardware-oriented Simple Active Counter algorithm to efficiently implement these counters;(2) it uses a distribution of the embedded memory, optimized towards maximum operating frequency. To the best of our knowledge, A-CM sketch outperforms all other FPGA-based sketch implementations.

关键词： Memory management Network intrusion detection Telecommunication traffic Approximation algorithms Data structures Throughput Probabilistic logic

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Assessment of RISC-V Processor Suitability for Satellite applications Invited Paper 21

Assessment of RISC-V Processor Suitability for Satellite App...

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21st ACM international conference on Computing Frontiers (CF)

作者： Vacca, Eleonora Cora, Giorgio Azimi, Sarah Sterpone, Luca Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy

ISBN: (纸本)9798400704925

This research addresses the challenges faced by space applications due to high-energy ionizing particles in the space environment, particularly when using commercial Off-The-Shelf (COTS) components like field programmable Gate Arrays (FPGAs) and soft-core processors like RISC-V. Our study introduces a methodology for evaluating the reliability of a state-of-the-art RISC-V processor intended for space missions, establishing a connection between space conditions, Single Event Upset (SEU) fault estimation, and emulation. Focusing on the space environment around a telecommunication satellite, we analyze particle fluxes and their impact on SRAM-based FPGAs using proton radiation test data. By integrating this data, we estimate the SEU rate per mission day caused by the specific radiation environment. Subsequently, we assess the suitability of the NEORV32 processor for operation in such an environment by implementing it in the target FPGA and conducting SEU emulation through fault injection campaigns. Our primary goal is to determine the design mean time to failure within the space environment where the processor is expected to function, a critical metric for implementing effective mitigation strategies for space mission designs. The obtained results, covering worst-case scenarios, suggest that RISC-V-based architectures prove resilient and adaptable for successful deployment in space missions.

关键词： FPGA Radiation Effects RISC-V Fault Injection GEO

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A Layout Area Reduction of Basic logic Element by Using a Neuron CMOS Type 4-input Variable logic Circuit 38

A Layout Area Reduction of Basic Logic Element by Using a Ne...

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38th IEEE Region 10 conference, TENCON 2023

作者： Ito, Shoma Sawada, Hisaya Furukawa, Hirotaka Hokari, Naruaki Nishiguchi, Daishi Fukuhara, Masaaki Graduate School of Information and Telecommunication Engineering Tokai University Tokyo Japan School of Information Telecommunication Engineering Tokai University Department of Embedded Technology Tokyo Japan Research Institute of Science and Technology Tokai University Kumamoto Japan

ISBN: (纸本)9798350302196

As field programmable Gate Arrays (FPGAs) become large integration, the area reduction of a Basic logic Element (BLE), which is a circuit for a logical definition in FPGAs, is required. We have studied a Variable logic Circuit (vVLC) using neuron CMOS inverters (vCMOSs) and have proposed a 4-input Variable logic Circuit (4-vVLC) as an alternative circuit against a 4-input Look-Up Table circuit (4-LUT) in the ordinary BLE. In this paper, we describe the 4-vVLC configuration and operations, and verify that the results of the HSPICE simulations and the theoretical performances are in general agreement. In addition, we design a layout of BLEs using 4-vVLC to reduce the BLE area and compare the 4-LUT and 4-vVLC. © 2023 IEEE.

关键词： Timing circuits

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Development and Deployment of programmable logic Controller-Based Switched Capacitor Banks to Enhance Power Factor of Three-Phase Induction Motors

Development and Deployment of Programmable Logic Controller-...

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2023 international conference on Emerging Power Technologies, ICEPT 2023

作者： Hamza, Amir Hamza, Mohammad Awais, Muhammad Ahmad, Faiza Rehman, Zahid Comsats University Islamabad Wah Campus Electrical & Computer Engineering Wah Cantt Pakistan Bahria University Islamabad Islamabad Campus Electrical Engineering Islamabad Pakistan University of Wah Electrical Engineering Wah Engineering College Wah Cantt Pakistan

ISBN: (纸本)9798350301014

In industries, three-phase inductive loads such as induction motors are widely used due to their low cost, easy maintenance, reliability, and robustness. Due to inductive loads, the power factor is reduced which results in the wastage of power, high billing costs, and penalties from electric power supply companies. In order to resolve this issue, a system has been designed for the power factor improvement of three-phase loads using the programmable logic controller (PLC) which will definitely minimize the operation cost of the plant, and also the demand for electricity supply on utility side will be reduced. The system is implemented by a combination of Hardware and software. The software consists of PLC programming whereas hardware consists of power and control circuits along with the protective devices. The programming of PLC is logic based which controls step by step sequence of operations. When the inductive load adds to the system, PLC will read the signal as an input from the contactor coil of the magnetic contactor connected with the motor and will send the signal as an output to the corresponding contactor coil of the magnetic contactor to switch the appropriate capacitor bank in order to improve the power factor. The experimental results for seven different cases utilized by different combinations of loads, without and with the use of the developed system have been discussed in this paper. So, from the perspective of energy management, we have always a need to improve the power factor of the Load. Due to many industrial control applications, the PLC is used as a power factor controller (PFC). © 2023 IEEE.

关键词： Induction motors

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Development of a Pellet Rotation System for Automated Visual Inspection

Development of a Pellet Rotation System for Automated Visual...

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international conference on Intelligent Manufacturing and Energy Sustainability, ICIMES 2023

作者： Reddy, B. Yeswanthkumar Reddy, K. Govardhan Vali, R. Hussain Mechanical Department JNTUA College of Engineering Pulivendula Pulivendula516390 India BSH Department Vigan Institute of Management and Technology for Women Hyderabad India Department of Mechanical Engineering Malla Reddy College of Engineering and Technology Hyderabad India

ISBN: (纸本)9789819967735

Nuclear power plants use uranium fuel, consisting of solid ceramic pellets of cylindrical shape with 18 mm diameter and 14 mm height, which are manufactured by various metallurgical processes. The pellets are placed on specially designed trays after grinding and pellet washing operations. These pellets are manufactured in large quantities and must confirm very stringent quality requirements usually prevalent in nuclear engineering applications. As part of quality checks on the fuel pellets, the operators manually check defects like fits, cracks, etc. occurring on the cylindrical surface. With the help of a machine vision system, the pellets were inspected by turning each pellet in its location itself while observing its surface for defects. The main equipment involves transferring system of pellets, a pellet rotation system, a vision system, a pellet retrieval system, and a system of rejection and recirculation of defective pellets. This paper mainly deals with the pellet rotation system. The design equipment has the provision to receive 5 pellets at 80 mm pitch, such that the axis of all the pellets is in the horizontal plane. They are rotated in their position in steps of 30 degrees such that in 12 steps the entire cylindrical surface will cover precisely. The cameras of the vision system were placed above each pellet with proper illumination. The programmable logic controller is used to control the pneumatic cylinders with proper intervals of time to accept or rejection of the pellet by the vision system. © 2024, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： programmable logic controllers

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