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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"
16760 条 记 录,以下是361-370 订阅
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ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED IN FPGA
ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED...
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18th international conference on field programmable and logic applications
作者: Fischer, Viktor Bernard, Florent Bochard, Nathalie Varchola, Michal Univ St Etienne CNRS UMR 5516 Lab Hubert Curien 18 Rue Prof Lauras St Etienne France Tech Univ Kosice Dept Elect & Multimedia Commun Kosice Slovakia
Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in field programmable Gate Arrays (FPGAs) employ the timing jitter from ring os... 详细信息
来源: 评论
An Implementation method of Poisson Image Editing on FPGA  27
An Implementation method of Poisson Image Editing on FPGA
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27th international conference on field programmable logic and applications (FPL)
作者: Maeda, Ryouhei Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Tennodai Tsukuba Ibaraki Japan
In this paper, we describe an FPGA system for the real-time processing of Poisson image Editing. Poisson Image Editing is a powerful method to overlay an image on another image seamlessly. In this method, however, a s... 详细信息
来源: 评论
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
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18th international conference on field programmable and logic applications
作者: Saegusa, Takashi Maruyama, Tsutomu Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058573 Japan
In image processing, FPGAs have shown very high performance in spite of their low operational frequency. This high performance comes from (1) high parallelism in applications in image processing, (2) high ratio of 8 b... 详细信息
来源: 评论
COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED DELAY MEASUREMENT METHOD
COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED...
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18th international conference on field programmable and logic applications
作者: Wong, Justin S. J. Cheung, Peter Y. K. Sedcole, Pete Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn Circuits & Syst Grp London SW7 2AZ England
The goal of this PhD project is to devise a way to combat the effect of process variation on propagation delays in modern FPGAs. Through our research, we have devised a novel measurement method that is capable of meas... 详细信息
来源: 评论
PERFORMANCE EVALUATION OF SPARSE MATRIX-MATRIX MULTIPLICATION
PERFORMANCE EVALUATION OF SPARSE MATRIX-MATRIX MULTIPLICATIO...
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23rd international conference on field programmable logic and applications (FPL)
作者: Jain-Mendon, Shweta Sass, Ron Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA
The conventional matrix multiplication algorithms that are suitable for dense matrices do not perform well on the corresponding Sparse Matrix-Matrix Multiplication (SMMM) operation. In particular, they do not utilize ... 详细信息
来源: 评论
AN AUTOMATIC FPGA DESIGN AND IMPLEMENTATION FRAMEWORK
AN AUTOMATIC FPGA DESIGN AND IMPLEMENTATION FRAMEWORK
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23rd international conference on field programmable logic and applications (FPL)
作者: Zhao, Qian Amagasaki, Motoki Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 860 Japan
Conventional FPGA design and implementation processes involve two separate flows. The FPGA architecture is determined by academic FPGA design flow. However, in the implementation phase, commercial VLSI design flow are... 详细信息
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Equivalence verification of FPGA and structured ASIC implementations
Equivalence verification of FPGA and structured ASIC impleme...
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17th international conference on field programmable logic and applications
作者: Pistorius, Joachim Hutton, Mike Schleicher, Jay Lotov, Mihail Julias, Enoch Tharmalingam, Kumara Altera Corp San Jose CA 95134 USA
Structured ASICs have recently emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. Though the structured ASIC fabric attacks mask and other fixed cost it does not solve ve... 详细信息
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A Partial Reconfiguration Controller for Altera Stratix V FPGAs  26
A Partial Reconfiguration Controller for Altera Stratix V FP...
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26th international conference on field-programmable logic and applications (FPL)
作者: Xiao, Zhenzhong Koch, Dirk Lujan, Mikel Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England
With the introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigura... 详细信息
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SHARED MEMORY HETEROGENEOUS COMPUTATION ON PCIE-SUPPORTED PLATFORMS
SHARED MEMORY HETEROGENEOUS COMPUTATION ON PCIE-SUPPORTED PL...
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23rd international conference on field programmable logic and applications (FPL)
作者: Shukla, Sambit K. Yang, Yang Bhuyan, Laxmi N. Brisk, Philip UC Riverside Riverside CA 92521 USA
Domain-disparity between CPU and Hardware Accelerators(HA) leads to CPU under-utilization and inter-domain data copy overheads. By exposing HA memory to OS and host MMU, these overheads can be eliminated. In this pape... 详细信息
来源: 评论
GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES
GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES
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19th international conference on field programmable logic and applications
作者: de Dinechin, Florent Klein, Cristian Pasca, Bogdan Univ Lyon LIP CNRS INRIA ENSLyon UCBL Ecole Normale Super Lyon F-69364 Lyon France
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application ... 详细信息
来源: 评论