In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. The framework can be integrated alongside the targeted...
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ISBN:
(纸本)9781467381239
In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. The framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).
In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in more realistic speeds allows much higher c...
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ISBN:
(纸本)9781467381239
In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. The main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. The first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the s...
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ISBN:
(纸本)9781424410590
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface to enable cross-platform application parallelism on reconfigurable hybrid cluster-on-chip systems and desktop cluster systems. The presented results are promising, showing the suitability, scalability and performance of parallelisation of image processing algorithms with a cross-platform MPI implementation.
Nowadays, Video-Based Navigation (VBN) is increasingly used in space-applications. The future space-missions will include this approach during the Entry, Descent and Landing (EDL) phase, in order to increase the landi...
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ISBN:
(纸本)9781479900046
Nowadays, Video-Based Navigation (VBN) is increasingly used in space-applications. The future space-missions will include this approach during the Entry, Descent and Landing (EDL) phase, in order to increase the landing point precision. This paper presents FEMIP: a high performance FPGA-based features extractor and matcher tuned for space applications. It outperforms the current state-of-the-art, ensuring a higher throughput and a lower hardware resources usage.
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The pattern matcher scans for patterns in ...
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ISBN:
(纸本)9781424403127
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The pattern matcher scans for patterns in high-speed streaming TCP data streams. The parser core augments each pattern found with semantic information determined from the patterns location within the data stream. The packet payload parser can provide a higher level of understanding of a data stream for many network applications. Such applications include high performance XML parsers, content-based/aware routers, and others. Additionally, a TCP processor allows stateful packet payload parsing of up to 8 million simultaneous TCP flows. The payload parser has been implemented in a Xilinx Virtex E 2000 FPGA on the field-programmable Port Extender platform. The parsing module runs,at 200 MHz and parse raw data at 6.4 Gbps. The payload parser, integrated with the TCP processor, runs at 100 MHz for a throughput of 3.2 Gbps.
The structure of the rocket-borne model is inherently complex, with processed images exhibiting high resolution and generating substantial amounts of data and calculations. Achieving robust real-time computing on an e...
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ISBN:
(数字)9798331531881
ISBN:
(纸本)9798331531898
The structure of the rocket-borne model is inherently complex, with processed images exhibiting high resolution and generating substantial amounts of data and calculations. Achieving robust real-time computing on an embedded platform poses significant challenges due to strictly limited resources, power consumption constraints, and size limitations. Our review of rocket-borne applications reveals considerable variability in the design resources of different devices, indicating a need for expanded design approaches. Upon evaluating existing methods, we identified two primary drawbacks. First, certain operators within the high-resolution target detection model are difficult to parallelize, resulting in significant inference delays that hinder the ability to meet task requirements. Although existing methods have been extended, there remains significant potential for performance enhancement in core scheduling for poor acceleration. This paper proposes an optimized architecture for the target detection algorithm accelerator designed for high-resolution images, along with a novel highly parallel data pre-processing and post-processing module implemented on FPGA to address these issues. Compared to the ARM implementation, this architecture demonstrates an improved performance of 24.64x. Furthermore, to ensure flexible application across various rocket launch scenarios, we introduce an optimization structure for convolution, pooling, and fusion operators and a multi-core expansion optimization method. This approach yields a 1.29x improvement in computing unit utilization compared to state-of-the-art multi-core scaling efforts. Finally, we assessed the accelerator architecture across multiple FPGA platforms, achieving a peak processing element utilization rate of 99.71% for a single core and layer. The overall computing efficiency, excluding the first layer, exceeded 90%. The peak computing power for the four cores reached 1638.4 GOPS, and the end-to-end computation time for
TCP/IP is widely used both in the Internet as well as in data centers. The protocol makes very few assumptions about the underlying network and provides useful guarantees such as reliable transmission, in-order delive...
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ISBN:
(纸本)9782839918442
TCP/IP is widely used both in the Internet as well as in data centers. The protocol makes very few assumptions about the underlying network and provides useful guarantees such as reliable transmission, in-order delivery, or control flow. The price for this functionality is complexity, latency, and computational overhead, which is especially pronounced in software implementations. While for Internet communication this is acceptable, the overhead is too high in data centers. In this paper, we explore how to optimize a TCP/IP stack running on an FPGA for data center applications with an emphasis on data processing (e.g., key value stores). Using a key-value store and a low-latency consensus protocol implemented on an FPGA as an example of the requirements that arise in data centers, we provide an extensive analysis of the overheads of TCP/IP and the solutions that can be adopted to minimize such an overhead. The proposed optimized TCP/IP stack minimizes tail latencies (a key metric in distributed data processing) and is efficiently implemented so as to be able to share the FPGA with application logic.
Many applications in image processing have high inherent parallelism. FPGAs have shown very high performance in spite of their low operational frequency by fully extracting the parallelism. In recent micro processors,...
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ISBN:
(纸本)9781424438914
Many applications in image processing have high inherent parallelism. FPGAs have shown very high performance in spite of their low operational frequency by fully extracting the parallelism. In recent micro processors, it also becomes possible to utilize the parallelism using multi-cores which support improved SIMD instructions, though programmers have louse them explicitly to achieve high performance. Recent GPUs support a large number of cores, and have a potential for high performance in many applications. However, the cores are grouped, and data transfer between the groups is very limited. Programming tools for FPGA, SIMD instructions on CPU and a large number of cores on GPU have been developed, but it is still difficult to achieve high performance on these platforms. In this paper, we compare the performance of FPGA, GPU and CPU using three applications in image processing;two-dimensional filters, stereo-vision and k-means clustering, and make it clear which platform is faster under which conditions.
Network security is increasing in importance as systems become more interconnected. Much research has been conducted on large appliances for network security, but these do not scale well to lightweight systems such as...
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ISBN:
(纸本)9781728148847
Network security is increasing in importance as systems become more interconnected. Much research has been conducted on large appliances for network security, but these do not scale well to lightweight systems such as those used in the Internet of Things (IoT). Meanwhile, the low power processors used in IoT devices do not have the required performance for detailed packet analysis. We present an approach for network intrusion detection using neural networks, implemented on FPGA SoC devices that can achieve the required performance on embedded systems. The design is flexible, allowing model updates in order to adapt to emerging attacks.
""We will demonstrate a portable FPGA tablet running a system-on-chip design featuring a 64-bit MIPS soft processor (BERI, Bluespec Extensible RISC Implementation) running the FreeBSD UNIX-derived OS. The de...
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ISBN:
(纸本)9781479900046
""We will demonstrate a portable FPGA tablet running a system-on-chip design featuring a 64-bit MIPS soft processor (BERI, Bluespec Extensible RISC Implementation) running the FreeBSD UNIX-derived OS. The demonstration has a graphical user interface which i""
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