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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16769 条记录，以下是371-380 订阅

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A Framework to Enable Runtime programmable P4-enabled FPGAs in the Open Cloud Testbed

A Framework to Enable Runtime Programmable P4-enabled FPGAs ...

引用

2023 IEEE INFOCOM conference on Computer Communications Workshops, INFOCOM WKSHPS 2023

作者： Han, Zhaoyang Handagala, Suranga Patle, Kalyani Zink, Michael Leeser, Miriam Northeastern University United States University of Massachusetts Amherst United States

ISBN: (纸本)9781665494274

This paper presents a framework for cloud users who wish to specify their experiments in the P4 language and map them to FPGAs in the Open Cloud Testbed (OCT). OCT consists of P4-enabled FPGA nodes that are directly connected to the network via 100 gigabit Ethernet connections, and which support runtime reconfiguration. Cloud users can quickly prototype and deploy their P4 applications through our framework, which provides the necessary infrastructure including a network interface shell for the P4 logic. We have provided several examples using this framework that demonstrate designs running at the 100 GbE line rate with the support of runtime reconfiguration for P4 functions. By combining an existing network interface shell and P4 toolchain on FPGAs, we offer a framework that enables users to rapidly execute their P4 experiments in real time on FPGAs. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Efficient Reinforcement Learning Framework for Automated logic Synthesis Exploration 21

Efficient Reinforcement Learning Framework for Automated Log...

引用

21st international conference on field-programmable Technology (ICFPT)

作者： Qian, Yu Zhou, Xuegong Zhou, Hao Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

logic synthesis is a crucial step in electronic design automation tools for integrated circuit design. In recent years, the development of reinforcement learning (RL) has enabled the designers to automatically explore the logic synthesis process. Existing RL based methods typically use conventional onpolicy models, which leads to data inefficiency. Moreover, the exploration approach for FPGA technology mapping in recent works lacks the flexibility of the learning process. In this work, we propose ESE, a reinforcement learning based framework to efficiently learn the logic synthesis process. The framework supports the modeling for both the logic optimization and the FPGA technology mapping. The reward functions and terminal conditions in the RL environment are designed to efficiently guide the optimization of the metrics and execution time. For the modeling of FPGA mapping, the logic optimization and technology mapping are combined to be learned in a flexible way. Moreover, the Proximal Policy Optimization model is adopted to improve the utilization of samples. The proposed framework is evaluated on several common benchmarks. For the logic optimization on the EPFL benchmark, compared with previous works, the proposed method obtains an 11.3% improvement in the average quality (node-level-product) and reduces the execution time by 13.7%. For the FPGA technology mapping on the VTR benchmark, our method improves the average quality (LUT-level-product) by 14.8%, and reduces the execution time by 14.4% compared with the recent work.

关键词： Measurement Integrated circuit synthesis Reinforcement learning Benchmark testing Minimization Integrated circuit modeling Task analysis

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You Only Get One-Shot: Eavesdropping Input Images to Neural Network by Spying SoC-FPGA Internal Bus 23

You Only Get One-Shot: Eavesdropping Input Images to Neural ...

引用

18th international conference on Availability, Reliability and Security (ARES)

作者： Thu, May Myat Real, Maria Mendez Pelcat, Maxime Besnier, Philippe Nantes Univ Univ Rennes CNRS INSA RennesIETRUMR 6164 F-35000 Rennes France

ISBN: (纸本)9798400707728

Deep learning is currently integrated into edge devices with strong energy consumption and real-time constraints. To fulfill such requirements, high hardware performances can be provided by hardware acceleration of heterogeneous integrated circuits (IC) such as System-on-Chip (SoC)-field programmable gate arrays (FPGAs). With the rising popularity of hardware accelerators for artificial intelligence (AI), more and more neural networks are employed in a variety of domains, involving computer vision applications. Autonomous driving, defence and medical domains are well-known examples from which the latter two in particular require processing sensitive and private data. Security issues of such systems should be addressed to prevent the breach of privacy and unauthorised exploitation of systems. In this paper, we demonstrate a confidentiality vulnerability in a SoC-based FPGA binarized neural network (BNN) accelerator implemented with a recent mainstream framework, FINN, and successfully extract the secret BNN input image by using an electromagnetic (EM) side-channel attack. Experiments demonstrate that with the help of a near-field magnetic probe, an attacker can, with only one inference, directly retrieve sensitive information from EM emanations produced by the internal bus of the SoC-FPGA. Our attack reconstructs SoC-FPGA internal images and recognizes a handwritten digit image with an average accuracy of 89% using a non-retrained MNIST classifier. Such vulnerability jeopardizes the confidentiality of SoC-FPGA embedded AI systems by exploiting side-channels that withstand the protection of chip I/Os through cryptographic methods.

关键词： Electromagnetic Side-Channel Near field Neural Network Image Processing System-on-Chip field programmable Gate Array On-chip Communication Bus

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Angle Measurement Method Based on Cross-Orthogonal Hall Sensor 16

Angle Measurement Method Based on Cross-Orthogonal Hall Sens...

引用

16th IEEE international conference on Electronic Measurement and Instruments, ICEMI 2023

作者： Chen, Xiao He, Xiran Zhang, Ying Gao, Bo Sichuan University Department of Physics Chengdu China

ISBN: (纸本)9798350327144

Angle measurement sensors have gained widespread application in fields of automobiles, machinery, and other industries. The cross-orthogonal architecture based on Hall sensors is proposed to position angle. Meanwhile, A novel angle calibration algorithm effectively reduces the error caused by the offset voltage, the unequal amplitude and the additional harmonics. A special FPGA test has been designed to measure the angle of rotation of the artificial magnetic field and verify the proposed methods. The angle measurement results show an average measured error of ± 1.263°, which can meet the requirements of industrial and practical applications. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA Implementation of High-Capacity SD Card using VHDL Language 21

FPGA Implementation of High-Capacity SD Card using VHDL Lang...

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21st international Multi-conference on Systems, Signals and Devices, SSD 2024

作者： Taha, Taha Basheer Ngadiran, Ruzelita Ehkan, Phaklen College of Applied Science Tishk International University Information Technology Department Erbil Iraq School of Computer and Communication Engineering Universiti Malaysia Perlis Perlis Malaysia

ISBN: (纸本)9798350374131

Limitations in capacity of internal memory chips on embedded systems lead to the usage of external memories especially when processing large amount of data as images or videos. FPGAs as embedded system devices used in different signal processing applications require extra memory for data storage. Current attempts in programming Secure Digital (SD) cards as external memories attached to FPGAs came with utilization of aiding application or of shelf tools which consumes large amount of chip clock cycles and reduce the overall performance. In this paper, a hardware implementation of SD card programming is presented by using pure and standalone VHDL code with high programming flexibility. In addition, High-Capacity SD cards (SDHC) are implemented for maximum storage capacity to handle large amount of data. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Configuration Security of FPGA in IoT Using logic Resource Protection

Configuration Security of FPGA in IoT Using Logic Resource P...

引用

international conference on Advances in Electrical and Computer Technologies, ICAECT 2021

作者： Meenakshi, S. Nirmala Devi, M. Department of Electronics and Communication Engineering Amrita School of Engineering Amrita Vishwa Vidyapeetham Coimbatore India

ISBN: (纸本)9789811911101

field-programmable gate arrays (FPGAs) consist of configurable logic blocks that have the reconfiguration property which provides the flexibility for the designer to reconfigure it for wide applications. In Internet of Things (IoT) applications which are being widely used, the FPGA platform is preferred for the realization, and hence, the IoT security is an important concern. In order to reduce the possibility of logic resource misuse, an efficient method to fill up the unused logic spaces is proposed which fills the configurable resources by using shift registers and a chain of gates, thereby eliminating the Hardware Trojan Horse (HTH) attacks on the application space. The additional structure does not cause the functional design framework to change. The filling up of the unutilized space does not incur any power overhead which is experimentally proved using IWLS and ISCAS’ 89 benchmark circuits implemented on Artix-7 FPGA board using Vivado design suite. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Internet of things

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RAPUF: A Novel Integration of Reversible logic and Arbiter Physical Unclonable Functions for Enhancing IoT Security

RAPUF: A Novel Integration of Reversible Logic and Arbiter P...

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2024 international conference on Artificial Intelligence, Computer, Data Sciences, and applications, ACDSA 2024

作者： Rizk, Dominick Rizk, Frederic Rizk, Patrick Rizk, Rodrigue The Catholic University of America Dept. of Electrical Engineering and Computer Science WashingtonDC United States University of Louisiana at Lafayette The Center for Advanced Computer Studies LafayetteLA United States University of Quebec at Trois-Rivières Dept. of Mechanical Engineering Drummondville Canada University of South Dakota Dept. of Computer Science VermillionSD United States

ISBN: (纸本)9798350394528

The Internet of Things (IoT) devices' proliferation underscores the critical importance of fortifying nanoscale circuit security against evolving cyber threats. This paper introduces an unprecedented paradigm to enhance IoT security through the synergistic integration of reversible logic gates and Arbiter Physical Unclonable Functions (APUFs). Reversible logic, known for its theoretical efficiency and energy conservation, is coupled with APUFs, leveraging their unique ability to exploit nanoscale manufacturing variations for robust hardware security. The novel integration is specifically tailored to address the distinctive security challenges prevalent in IoT ecosystems. The proposed methodology encompasses designing and implementing a secure nanoscale circuit system, tailored to the resource constraints of IoT devices. Through an exhaustive literature review, we establish the significance of reversible logic and APUFs in the broader context of nanoscale circuit design and IoT security. The experimental results demonstrate not only the feasibility of the integrated approach but also its effectiveness in fortifying IoT devices against unauthorized access and data breaches. This research contributes a fresh perspective to the field of IoT security, presenting a novel solution that combines energy-efficient reversible logic with the intrinsic security features of APUFs. The outcomes of this work hold promise for advancing the security paradigm of IoT devices ensuring their resilience against emerging threats in the ever-evolving landscape of cybersecurity and contributing significantly to the evolving field of quantum-enhanced IoT security. © 2024 IEEE.

关键词： Internet of things

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Educational Platform for Closed Loop AC Variable Speed Drive based on programmable logic Controller 11

Educational Platform for Closed Loop AC Variable Speed Drive...

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11th IEEE international conference on Renewable Energy Research and applications, ICRERA 2022

作者： Cirstoiu, Adelina NMaria Chirila, AurelnIonut Deaconu, Ioan NDragos Universitatea Politehnica Din Bucureşti Electrical Engineering Faculty Bucureşti Romania

ISBN: (数字)9781665471404

ISBN: (纸本)9781665471404

This paper describes a variable speed drive system that controls the speed of an induction motor using a frequency inverter controlled by a PLC (programmable logic Controller). The system is applicable to renewable systems such as photovoltaic panels, telecommunication systems, which rotate easily, and high inertia driving systems such as oil and gas drilling gaskets. For these industrial applications the maximum shaft rotating speed is low value (e.g., about 250 rpm). As the mechanical time constants of the system are high, the students can leisurely follow the process of closed loop shaft rotating speed control, because the article is used for educational purposes. The PID control method is proved using PLCs due to their frequent presence among various automated industrial processes. © 2022 IEEE.

关键词： Variable speed drives

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Hardware Implementation of Posit Numeration System using FPGA for Signal Processing applications 7

Hardware Implementation of Posit Numeration System using FPG...

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7th international conference on Trends in Electronics and Informatics, ICOEI 2023

作者： Alapati, Madhu Sravya Swain, Raghunandan Panigrahy, Asisa Kumar Gokaraju Rangaraju Institute of Engineering and Technology Dept.of Ece Hyderabad India Parala Maharaja Engineering College Dept. of Etc Odisha India

ISBN: (纸本)9798350397284

Posit numeration system is a type 3 Unum system format that was introduced in 2017. It has a wide range of applications in digital signal processing. Data can be transferred in either binary or analog format. As a newly introduced number system, it currently has a very limited range of applications and will gradually expand its capabilities in all other domains. It can be used as a replacement for the IEEE 754 floating point number system in the future. To accomplish this, this study begins with a small step: some posit applications are executed in verilog HDL language, i.e., developing verilog code to convert a number from floating point to posit, as well as to convert a number from posit to floating point, using 32-bit numbers. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with...

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international conference on field programmable logic and applications

作者： Kenneth Liu Alec Lu Zhenman Fang HiAccel Lab Simon Fraser University Burnaby B.C Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

The Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration, and can no longer match the increasing data rates offered by modern *** support large Bloom filters with low false-positive rate and high throughput, we present BitBlender, a configurable and scalable multi-input-stream Bloom filter acceleration framework in HLS. To effectively share one large bit-vector on chip among all streams, we design and implement the novel arbiter and unshuffle modules to dynamically schedule conflicting accesses to execute sequentially and non-conflicting accesses to execute in parallel. To support different user configurations of the Bloom filter, we also develop an automation flow, together with an accurate performance estimator, to automatically generate the best BitBlender design. Experimental results show that, on the AMD/Xilinx Alveo U280 FPGA, BitBlender achieves a throughput up to 2,194 MQueries/s (i.e., $8.8 \mathrm{~GB} / \mathrm{s}$) for a $\mathrm{9 6 M b}$ bit-vector with 0.01% false-positive rate. It achieves up to 10.4x speedup over a 24-thread CPU implementation and up to 4.9x speedup over a naively-duplicated multi-stream FPGA design. BitBlender will be released soon at https://***/SFU-HiAccel/BitBlender.

关键词： Matched filters Schedules Automation Prevention and mitigation System recovery Throughput System-on-chip logic field programmable gate arrays Streams

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