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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16770 条记录，以下是391-400 订阅

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SpaceCube GHOST: A Resilient Processor for Low-Power, High-Reliability Space Computing

SpaceCube GHOST: A Resilient Processor for Low-Power, High-R...

引用

IEEE Aerospace conference

作者： Perryman, Noah Franconi, Nicholas Crum, Gary Wilson, Christopher George, Alan D. Univ Pittsburgh Dept Elect & Comp Engn NSF Ctr Space High Performance & Resilient Comp S 4420 Bayard StSuite 560 Pittsburgh PA 15213 USA NASA Goddard Space Flight Ctr Sci Data Proc Branch Software Engn Div Code 5878800 Greenbelt Rd Greenbelt MD 20771 USA

ISBN: (纸本)9798350304626

There is a direct need for high-visibility NASA missions that provide significant scientific impact or have a high mission class using completely radiation-hardened (rad-hard) electronics solutions, to enable artificial intelligence (AI) applications in harsh environments despite severe size, weight, and power (SWaP) constraints. For these missions, where current state-of-the-art solutions are too power-demanding or are incapable of surviving the intended radiation environment, an alternative rad-hard processing architecture that can leverage the control-flow capabilities of scalar processors while also incorporating the hardware-acceleration capabilities of an FPGA is of significant value. Therefore, in this research, we propose a miniaturized (3.5 in. Chi 3.5 in. form factor) processor card featuring the GR740 quad-core rad-hard processor and the CertusPro-NX-RT radiation-tolerant FPGA, called the SpaceCube GR740 Host for Onboard Science and Telemetry (GHOST) architecture. The card will be designed to conform to the NASA Goddard Space Flight Center (GSFC) CubeSat Card Specification (CS2), which provides a common template to build new 1U CubeSat-sized cards compatible with a variety of other avionics designs. The GR740 features a fault-tolerant quad-processor LEON4FT SPARC V8 integer unit with a 7-stage pipeline and 4 Chi 4 KiB instruction and data caches. To extend the capabilities of the GR740, the CertusPro-NX-RT, a low-power radiation-tolerant FPGA, was combined to create a hybrid system architecture, providing the benefits of a programmable logic fabric. The GHOST architecture supports high-reliability, general-purpose processing and system monitoring via the GR740 while simultaneously increasing the AI-based application performance via a combination of the GR740 and CertusPro-NX-RT.

关键词： field programmable gate arrays (FPGA)

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HDL-Based Smart Home Implementation Using FSM logic and FPGA 11

HDL-Based Smart Home Implementation Using FSM Logic and FPGA

引用

11th international conference on Internet of Everything, Microwave Engineering, Communication and Networks, IEMECON 2023

作者： Sen, Soumya Saha, Souvik Dasgupta, Agnibha Dr. B. R. Ambedkar National Institute of Technology Dept. of Electronics & Communication Engineering Jalandhar India University of Engineering & Management Dept. of Electronics & Communication Engineering Jaipur India Maulana Abul Kalam Azad University of Technology Dept. of Microelectronics & Vlsi Technology West Bengal India

ISBN: (纸本)9781665475129

Every aspect of the modern world is powered by technology. The development of more advanced technology has led to the creation of more sophisticated electronic devices. The automation of homes is quickly becoming one of the most intelligent uses of technology. Regarding home automation, the two most important considerations are safety and privacy. Regarding safety, it includes temperature management and lighting. The security system recognizes the door-entry intruders and the fire. The field Programming Gate Array (FPGA) is interfaced with by the devices and sensors to control it. This smart home was designed using a digital platform. Utilizing Finite State Machine (FSM) principles In Xilinx 14.7 and ModelSim 6.4, Verilog has been synthesized, and an Resistor Transistor logic (RTL) schematic has been applied to depict the pin layout. The FPGA Spartan 3 board is used to obtain, verify, and create the simulated waveforms. This extreme flexibility of the system enables the addition of novel devices and monitoring of essential equipment. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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programmable Synchronous 2-Bit Counter in Quantum-Dot Cellular Automata 4

Programmable Synchronous 2-Bit Counter in Quantum-Dot Cellul...

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2023 4th international conference on Electrical, Electronic Information and Communication Engineering, EEICE 2023

作者： Cui, Huanqing Yang, Xiaokuo Wei, Bo Zhang, Mingliang Dou, Shuqing Xia, Yongshun Fundamentals Department Air Force Engineering University Xi'an710051 China Air Force Communications Non-Commission Officer Academy Dalian116100 China

Quantum-dot Cellular Automata (QCA) is a newly-developed nanoscale electron device that has the potential to replace the conventional transistor in the future. Owing to the unique field-coupling mechanism of QCA, several constraints must be fulfilled during the design of QCA sequential circuits, which makes the construction of sequential circuits a relatively intractable issue in QCA research. In this paper, a programmable synchronous 2-bit counter in QCA is proposed, which is consisted of combinational logic and falling edge-triggered JK flip-flops. The count mode of the programmable counter can be changed on-demand by mode control signals. Moreover, an initial state setting method of the QCA circuit is also proposed during the design of the counter so that the effects of random initial states can be avoided. Simulation with QCADesigner software demonstrates the validity of the proposed counter. © Published under licence by IOP Publishing Ltd.

关键词： Nanocrystals

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Implementation of Ultra High Definition Video Output with Zynq-7000 for CNC Machines and Industrial Equipment

Implementation of Ultra High Definition Video Output with Zy...

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2023 international conference on Industrial Engineering, applications and Manufacturing, ICIEAM 2023

作者： Popov, Maksim Orlova, Kseniya Romanov, Aleksandr Bigprinter Digital Innovations Llc Department of Research and Development Moscow Russia Hse University Moscow Russia

ISBN: (纸本)9781665475952

The article presents a method of video output subsystem's development with an ultra-high resolution (2560 x 1440 pixels and higher) support, a method for assessing the permissible video mode parameters and setting drivers, as well as an example of successful implementation of such a subsystem based on entry-level chips of the Zynq-7000 family. The features of a hardware platform definition in the Vivado environment and the Petalinux operational system configuration and setup are described. The results of the subsystem's test runs using various video modes are presented, including horizontal and vertical resolution value as well as a frame refresh rate. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Research on logic Loading Process and Signal Integrity based on Prom 2

Research on Logic Loading Process and Signal Integrity based...

引用

2022 2nd international conference on Mechanical Automation and Electronic Information Engineering, MAEIE 2022

作者： Sun, Pei Ji, Jin Guo, Jingtao Fan, Xinming Xi'An Aeronautics Computing Technique Research Institute AVIC Xi'an China

a certain embedded product failed to load FPGA configuration occasionally when it was powered on. In order to determine the cause of the failure, the principle of FPGA configuration circuit was studied, and the possible causes of the failure were analyzed. Through testing, theoretical analysis and comprehensive simulation, it was finally determined that the layout of CCLK matching resistance was unreasonable, which led to the wrong loading of configuration data caused by CCLK false edge acquisition. Finally, the corrective measures are proposed for the fault, and the test shows that the measures are reasonable and effective. © Published under licence by IOP Publishing Ltd.

关键词： field programmable gate arrays (FPGA)

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High-precision pulse width generation technology based on high-speed DAC

High-precision pulse width generation technology based on hi...

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2024 international conference on Mechatronic Engineering and Artificial Intelligence, MEAI 2024

作者： Wang, Ruichuang Zhang, Minghu Feng, Zhiguang Zhou, Houping Wuhan Digital Engineering Institute Wuhan430205 China College of Intelligent Science and Engineering Harbin Engineering University Harbin150001 China

ISBN: (纸本)9781510689176

The pulse width parameter of integrated circuits is an important technical indicator for measuring the system's high-speed performance and rapid response capabilities, directly affecting the device's response speed and accuracy. Achieving traceability of integrated circuit time characteristic parameters is fundamental to ensuring the core performance of the system. The pulse width calibration device for integrated circuit testing systems calibrates the system by reproducing the behavior model of the parameters. Traditional waveform generation methods typically rely on cyclical reading of waveform memory, resulting in complex system designs, high storage resource usage, and lower waveform accuracy. To address these issues, a standard pulse width and rise/fall time waveform generation module based on an "FPGA + DAC" architecture has been designed. By directly utilizing the timing logic resources of the FPGA, multiple data modules are set up to generate waveform data in parallel, making waveform parameter adjustment more flexible and reducing waveform generation response time. Additionally, with the integration of an internal time parameter correction module, the accuracy and stability of the generated signal's time parameters are further improved, meeting the requirements for high-precision calibration. © 2025 SPIE.

关键词： Data conversion Pulse signals Clocks Calibration Integrated circuits field programmable gate arrays Signal generators Error control coding System integration Interference (communication)

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Smart Load Optimisation Overload And Short Circuit Fault Monitoring using programmable logic Controller & SCADA

Smart Load Optimisation Overload And Short Circuit Fault Mon...

引用

Soft Computing for Security applications (ICSCSA), international conference on

作者： Debraj Bhowmick Hrushikesh V. Adling Amol B. Kawade Dipesh Pardeshi Department of Electrical Engineering Sanjivani College of Engineering Kopargaon A.Nagar India

ISBN: (数字)9798331515720

ISBN: (纸本)9798331515737

This research presents a real-time automatic control system for ensuring reliable power supply in distributed generation systems. Leveraging programmable logic Controllers (PLCs) and Supervisory Control and Data Acquisition (SCADA), the system prioritizes and dynamically switches loads based on available power sources. By utilizing ladder logic for PLC programming and SCADA for centralized monitoring, the system effectively manages power distribution and minimizes manual intervention. Demonstrated in industrial settings, this approach enhances operational efficiency and reliability, particularly in regions prone to power outages.

关键词： Power supplies programmable logic devices SCADA systems Power distribution Real-time systems Power grids Circuit faults Security Sustainable development Monitoring

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FPGA-Based Adaptive Traffic Management System for Optimizing Five-Point Intersection Flow

FPGA-Based Adaptive Traffic Management System for Optimizing...

引用

international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Supratim Nandi Atalanta Pal Oishi Banerjee Wrishav Das Sumit Barnwal Soumik Kumar Kundu Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

The present invention relates to an FPGA driven traffic management system specifically designed for five-point intersections, which are notably complex due to their unique traffic flow patterns. FPGA is field programmable gate of array basically used to implement digital virtual logic into real hardware. Here FPGAs are utilized to process and control this system periodically every 360 sec durations. This innovative approach not only improves traffic flow and reduces waiting times but also contributes to handle emergency like situation and according to that manipulate signals. The adaptability of the invention to diverse traffic conditions makes it a robust solution for urban traffic management challenges.

关键词： Technological innovation Costs VHDL Pedestrians Process control programmable logic arrays logic gates Traffic control Software field programmable gate arrays

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TCAM-Hash: A Combined Routing Lookup for Network applications 5

TCAM-Hash: A Combined Routing Lookup for Network Application...

引用

5th international conference on Electronic Engineering and Informatics, EEI 2023

作者： Zhang, Keran Huang, Wenjun Kuang, Nailiang Zhong, Sheng Liang, Yong Luo, Hangzai Xi'an Microelectronics Technology Institute Xi'an China Northwest University of China Xi'an China

ISBN: (纸本)9798350327076

The latency and resource consumption are significant factors for routing lookup (RL) in network applications. This paper proposes a combined RL strategy (TCAM-Hash), which utilizes the advantages of both TCAM- based and hash-based RL. The hash module solves the RL for over 90% of network rules. The TCAM module solves the RL for the rest rules. In the FPGA experiment, the hash module supports the RL for wide input rules (144-bit), achieves very low latency (12.8 ns), and costs very limited FPGA resources (2.5 BRAM and 664 LUT). © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth Memory

H2PIPE: High Throughput CNN Inference on FPGAs with High-Ban...

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international conference on field programmable logic and applications

作者： Mario Doumet Marius Stan Mathew Hall Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto Canada Microsoft Redmond USA Vector Institute Toronto Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Convolutional Neural Networks (CNNs) combine large amounts of parallelizable computation with frequent memory access. field programmable Gate Arrays (FPGAs) can achieve low latency and high throughput CNN inference by implementing dataflow accelerators that pipeline layer-specific hardware to implement an entire network. By implementing a different processing element for each CNN layer, these layer-pipelined accelerators can achieve high compute density, but having all layers processing in parallel requires high memory bandwidth. Traditionally this has been satisfied by storing all weights on chip, but this is infeasible for the largest CNNs, which are often those most in need of acceleration. In this work we augment a state-of-the-art dataflow accelerator (HPIPE) to leverage both High-Bandwidth Memory (HBM) and on-chip storage, enabling high performance layer-pipelined dataflow acceleration of large CNNs. Based on profiling results of HBM’s latency and throughput against expected address patterns, we develop an algorithm to choose which weight buffers should be moved off chip and how deep the on-chip FIFOs to HBM should be to minimize compute unit stalling. We integrate the new hardware generation within the HPIPE domain-specific CNN compiler and demonstrate good bandwidth efficiency against theoretical limits. Compared to the best prior work we obtain speed-ups of at least $19.4 \mathrm{x}, 5.1 \mathrm{x}$ and 10.5 x on ResNet-18, ResNet-50 and VGG-16 respectively.

关键词： Memory management Bandwidth System recovery Throughput Hardware System-on-chip Convolutional neural networks Kernel Engines field programmable gate arrays

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