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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16760 条记录，以下是401-410 订阅

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A Novel Wavy Channel Gate-All-Around FETs for Next-Generation CMOS applications 23

A Novel Wavy Channel Gate-All-Around FETs for Next-Generatio...

引用

IEEE 23rd international conference on Nanotechnology (NANO)

作者： Haider, Ranita Das, Uttam Kumar Ansari, Md. Hasan Raza El-Atab, Nazek King Abdullah Univ Sci & Technol KAUST Smart Adv Memory Devices & Applicat SAMA Labs Comp Elect & Math Sci & Engn Div CEMSE Elect & Comp Engn Program Thuwal 239556900 Saudi Arabia

ISBN: (纸本)9798350333466

The work presents a novel wavy channel nanosheet field effect transistor (WCNSFET) and its circuit-level performance. In this work, a single nanosheet is transformed into a wave-like structure to enhance the physical device area, thus showing an improvement in device performance. The device and circuit level performances are analyzed using 3D TCAD simulation tools. Furthermore, the wavy channel nanosheet FETs are analyzed with different number of waves in a single sheet and compared with flat sheet-based transistors for different channel materials (Ge and GaAs). The results reveal the improvement in drive current, low propagation delay, a smooth voltage transfer characteristic, high noise margin, and low energy. The results achieved with this novel device make the device a promising candidate for next-generation low power CMOS applications.

关键词： Gate All Around (GAA) wavy channel logic application simulation Inverter

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Deploying Post-quantum Algorithms in Existing applications and Embedded Devices 3rd

Deploying Post-quantum Algorithms in Existing Applications a...

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3rd international conference on Ubiquitous Security (UbiSec)

作者： Muzikant, Petr Willemson, Jan Cybernetica AS Maealuse 2-1 EE-12618 Tallinn Estonia

ISBN: (纸本)9789819712731;9789819712748

This document studies the current state of post-quantum cryptography implementation feasibility, providing general approaches that developers and security engineers can utilize to start integrating today. First, we analyze the current state of the art in the field of available cryptographic libraries and standards for algorithm interpretations and encodings. Then, we provide few implementation challenges that rose from our experiments and how to handle them. Lastly, we have built a proof-of-concept implementation by creating a post-quantum version of a modern web authentication framework. Our work introduces post-quantum support in multiple open-source libraries that together enable web-service administrators to authenticate their users with Dilithium-5 or Falcon-1024 secured electronic identities. Among other components, our proof-of-concept also includes a client side solution for key management using programmable embedded device.

关键词： Post-Quantum Cryptography Integration Authentication Embedded Development Post-Quantum Implementation Dilithium Falcon

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Reliability Analysis and Evaluation of PLC's Functional Diagrams

Reliability Analysis and Evaluation of PLC's Functional Diag...

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international conference on Computer and applications (ICCA)

作者： Amin Al Ka'bi Khaled AbuJbara Electrical and Electronics Engineering Department Australian University Kuwait Kuwait City Kuwait

ISBN: (数字)9798350367560

ISBN: (纸本)9798350367577

In industrial electronic systems, programmable logic controllers, or PLCs, find widespread application. Reliability becomes a key difficulty in safety-sensitive applications as system complexity increases. This paper presents a prescribed modeling and validation approach of the functional blocks in PLC's logic diagrams, and a logic specification system formalizes the functional block diagrams. We take up the subject of equivalency checking, which arises often when comparing design implementations with varying performance restrictions. We provide a novel approach to show the equivalency in a higher-order logic theorem proving system by utilizing a potent co-induction proof strategy via simulation. We provide a real-world example from industrial environment with essential scenarios to verify the efficacy of our technique. Our approach's completeness and soundness are supported.

关键词： Industrial electronics Technological innovation Computational modeling programmable logic devices Reliability theory Real-time systems Filling Safety logic Motion control

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Active Antenna Concept in Small Satellite applications 8

Active Antenna Concept in Small Satellite Applications

引用

Joint 8th international conference on Digital Arts, Media and Technology and 6th ECTI Northern Section conference on Electrical, Electronics, Computer and Telecommunications Engineering, ECTI DAMT and NCON 2023

作者： Nedelchev, Marin Technical University of Sofia Department of Radiocommunications and Videotechnologies Sofia Bulgaria

ISBN: (纸本)9798350396546

Satellite communications using small satellites is one of the driving forces of the modern society with applications including weather monitoring and forecast, space exploration, telecommunications, high speed data transfer. These applications require constant communication between the satellite and the Earth, which can be a challenge for conventional communication modules and antennas. The current digital back-end realization is based on field-programmable gate array with SDR based radio frequency back end in one module. This configuration arises a lot problems connected to the heat dissipation, electromagnetic compatibility, higher mechanical requirements, and power loss in the cables. This paper proposes active antenna approach to small satellite applications in order to overcome the aforementioned drawbacks of the current configuration. © 2023 IEEE.

关键词： Space research

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IoT-Based Recommendation System for Citrus Land Suitability Using Mamdani Fuzzy logic

IoT-Based Recommendation System for Citrus Land Suitability ...

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2024 Beyond Technology Summit on Informatics international conference, BTS-I2C 2024

作者： Cahyanto, Triawan Adi Sufianto, Genta Handayani, Luluk Rosyidah, Ulya Anisatur Yanuarti, Rosita Amiri, Yusril Izzi Arlisa Universitas Muhammadiyah Jember Department of Informatics Engineering Jember Indonesia Universitas Muhammadiyah Jember Department of Information System Jember Indonesia

ISBN: (纸本)9798331508579

The rapid growth of Internet of Things (IoT) technology has enabled innovative applications in agriculture, addressing critical challenges faced by farmers. This study proposes designing and implementing an IoT-based recommendation system for citrus land suitability using the Mamdani fuzzy logic. The system integrates real-time data collection from environmental sensors, cloud-based storage, and fuzzy logic processing to generate actionable farmer recommendations. Key parameters such as temperature, soil moisture, and light intensity are collected using IoT sensors and processed to categorize land suitability into 'Highly Suitable,' 'Moderately Suitable,' and 'Not Suitable' levels. field tests with over 2,500 data points demonstrated a 92% match rate with expert evaluations, validating the system's accuracy and reliability. Farmers positively received the system's usability, highlighting its potential to enhance decision-making and optimize citrus cultivation. © 2024 IEEE.

关键词： Smart agriculture

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An Improved Octet Itoh-Tsujii Algorithm for FPGA Platforms

An Improved Octet Itoh-Tsujii Algorithm for FPGA Platforms

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2023 international conference on Energy, Materials and Communication Engineering, ICEMCE 2023

作者： Sanjana, A. Venkatasubramani, V.R. Rajaram, S. Kalaiarasi, M. Manikandan, M.S.K. Vinoth Thyagarajan, V. Thiagarajar College of Engineering Dept. of Ece Madurai India Ceremorphic Technology Hyderabad India

ISBN: (纸本)9798350393378

Itoh-Tsujii algorithm is used to compute the multiplicative inverse over GF(2m) in cryptographic applications like Elliptic Curve Cryptography (ECC). The most intricate process that affects the general flow of the process is the computation of the modular inverse. With the focus on the NIST irreducible trinomial field GF (2193), this work presents a novel octet Itoh-Tsujii algorithm designed to minimize the complexity of multiplicative inverse operation for hardware implementation. Analysis of the outcomes reveals that the suggested algorithm increases performance while lowering complexity. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-Implemented Reconfigurable logic Locking Using N-Stage Delays for Obfuscation

FPGA-Implemented Reconfigurable Logic Locking Using N-Stage ...

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IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Saurabh Srivastava Sangeeta Nakhate Dept. of ECE Maulana Azad National Institute of Technology Bhopal India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

System security is becoming an increasingly essential feature of modern computing systems, particularly programmable hardware such as field programmable Gate arrays (FPGA), employed in various applications such as autonomous systems and digital networks. However, safeguarding FPGA-based devices against IP theft and reverse engineering is difficult and a big concern for the semiconductor and defense industries. Previously, various obfuscation approaches such as gate level obfuscation, camouflaging, and strong puff were employed to make a distinct key for every chip. These designs, however, are more area-intensive, consume more power, and are easier to crack the key. In this research, we propose a novel obfuscation idea that integrates a reconfigurable hardware obfuscation block into the original circuit with an additional N-stage Delay circuit to enhance overall system security and resistance to threats. The present idea relates to the increase in the security of the system against the piracy, overbuilding and from the cloning and camouflaging of the chip. The proposed technique does not have any bulky circuit, and it is easily realizable and just requires some additional modules that can easily reconfigured with a very smaller area and power overhead thereby offering performance benefits and increasing the time of sat attack iteration, making the locking system more complex and difficult to decode.

关键词： Resistance Power measurement Defense industry Hardware security Reverse engineering Reconfigurable logic logic gates Delays IP networks field programmable gate arrays

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Design of a high speed rat whiskers tracking and symmetry analysis system based on FPGA

Design of a high speed rat whiskers tracking and symmetry an...

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45th Annual international conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Wang, Xuecheng Zhao, Ziyao Liu, Yang Zhang, Milin Zhao, Zhe Tsinghua Univ Dept Elect Engn Beijing Peoples R China Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol Beijing Peoples R China Tsinghua Univ Inst Precis Med Beijing Peoples R China Tsinghua Univ Beijing Tsinghua Changgung Hosp Dept Orthoped Beijing Peoples R China

ISBN: (纸本)9798350324471

This paper presents a high-speed rat whisker tracking and symmetry analysis system based on FPGA. The system utilizes high-speed image sensors recording rat face videos at 120 and 1000 fps. The Xilinx Ultra96 single computer board is chosen as the platform to implement the system's processing system (PS) and the programmable logic (PL) part. The PL part is responsible for high-speed image processing and whisker tracking, while the PS part analyzes the symmetry of rat face using the tracking results from the PL part. With a processing speed FoM of 118.5 fps/GHz on the Xilinx Ultra96 single computer board and 275.47 fps/GHz on a laptop with Intel Core i5-11500T@1.5GHz, the presented system achieves excellent performance. The proposed whisker detection method has a precision of 98.2% when a threshold with a 4-degree error is selected, with an average error angle of 0.98 degrees across more than 10,000 video frames. Moreover, the proposed system is capable of local video processing within millisecond delays. These results demonstrate the feasibility of developing a high-speed, accurate, and efficient whisker tracking and symmetry analysis system for rat behavior research.

关键词： field programmable gate arrays (FPGA)

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DRRA-based Reconfigurable Architecture for Mixed-Radix FFT 36

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT

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36th international conference on VLSI Design (VLSID) / 22nd international conference on Embedded Systems (ES)

作者： Kallapu, Reeshita Siathist, Dimitrios Hoppe, Srinivas Henlanit, Ahmed Indian Inst Technol Bhubaneswar IITBBS Sch Elect Sci Bhubaneswar India Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9798350346787

Fast-Fourier Transform is an important algorithm which is used in digital signal processing and communication applications. Furthermore, mixed-radix FFT provides flexibility and increases the speed of FFT computation. For real-time processing, efficient hardware implementation using reconfigurable architectures is preferred which can offer higher performance and flexibility. In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also providing the flexibility to select the radix for each stage of the FFT. The twiddle factor generator proposed in this architecture minimizes the memory requirements and simplifies the hardware. Using the proposed architecture, various length FFTs were mapped onto either single cell or multiple cells in parallel. It is observed that the proposed architecture improves the performance by 2x times when compared to the existing FFT architectures.

关键词： Fast Fourier Transform FFT butterfly radix 2 & 4 Coarse Grain Reconfigurable Architectures field programmable Gate Array

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Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

Fast Switching Activity Estimation for HLS-Produced Dataflow...

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international conference on field programmable logic and applications

作者： Jiantao Liu Maksymilian Graczyk Andrea Guerrieri Lana Josipović Department of Information Technology and Electrical Engineering ETH Zurich Zurich Switzerland EPFL School of Computer and Communication Sciences Lausanne Switzerland HES-SO School of Engineering Sion Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction level they operate on typically contains no or limited information on low-level circuit details that power consumption depends on. Dataflow circuits have recently been explored in the HLS context; apart from their ability to achieve performance that is superior to standard HLS-generated circuits, their well-defined structure and computational model offer entirely new opportunities for reasoning about power at the HLS level. This paper exploits this insight to present an accurate switching activity estimator for HLS-produced dataflow circuits. Our estimator combines the knowledge about the dataflow circuit structure with software profiling and detailed glitching analysis to estimate the circuit’s switching activity with an average error rate of 1.8% and average speedup of $17.8 \times$ compared with a cycle-accurate simulator. Our technology-agnostic solution makes a critical advancement in HLS power estimation and sets the stage for integrating power optimization within the HLS process.

关键词： Measurement Accuracy Power demand Estimation Hardware Software logic Optimization Standards Switching circuits

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