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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16770 条记录，以下是411-420 订阅

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Design of a high speed rat whiskers tracking and symmetry analysis system based on FPGA

Design of a high speed rat whiskers tracking and symmetry an...

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45th Annual international conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Wang, Xuecheng Zhao, Ziyao Liu, Yang Zhang, Milin Zhao, Zhe Tsinghua Univ Dept Elect Engn Beijing Peoples R China Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol Beijing Peoples R China Tsinghua Univ Inst Precis Med Beijing Peoples R China Tsinghua Univ Beijing Tsinghua Changgung Hosp Dept Orthoped Beijing Peoples R China

ISBN: (纸本)9798350324471

This paper presents a high-speed rat whisker tracking and symmetry analysis system based on FPGA. The system utilizes high-speed image sensors recording rat face videos at 120 and 1000 fps. The Xilinx Ultra96 single computer board is chosen as the platform to implement the system's processing system (PS) and the programmable logic (PL) part. The PL part is responsible for high-speed image processing and whisker tracking, while the PS part analyzes the symmetry of rat face using the tracking results from the PL part. With a processing speed FoM of 118.5 fps/GHz on the Xilinx Ultra96 single computer board and 275.47 fps/GHz on a laptop with Intel Core i5-11500T@1.5GHz, the presented system achieves excellent performance. The proposed whisker detection method has a precision of 98.2% when a threshold with a 4-degree error is selected, with an average error angle of 0.98 degrees across more than 10,000 video frames. Moreover, the proposed system is capable of local video processing within millisecond delays. These results demonstrate the feasibility of developing a high-speed, accurate, and efficient whisker tracking and symmetry analysis system for rat behavior research.

关键词： field programmable gate arrays (FPGA)

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DRRA-based Reconfigurable Architecture for Mixed-Radix FFT 36

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT

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36th international conference on VLSI Design (VLSID) / 22nd international conference on Embedded Systems (ES)

作者： Kallapu, Reeshita Siathist, Dimitrios Hoppe, Srinivas Henlanit, Ahmed Indian Inst Technol Bhubaneswar IITBBS Sch Elect Sci Bhubaneswar India Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9798350346787

Fast-Fourier Transform is an important algorithm which is used in digital signal processing and communication applications. Furthermore, mixed-radix FFT provides flexibility and increases the speed of FFT computation. For real-time processing, efficient hardware implementation using reconfigurable architectures is preferred which can offer higher performance and flexibility. In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also providing the flexibility to select the radix for each stage of the FFT. The twiddle factor generator proposed in this architecture minimizes the memory requirements and simplifies the hardware. Using the proposed architecture, various length FFTs were mapped onto either single cell or multiple cells in parallel. It is observed that the proposed architecture improves the performance by 2x times when compared to the existing FFT architectures.

关键词： Fast Fourier Transform FFT butterfly radix 2 & 4 Coarse Grain Reconfigurable Architectures field programmable Gate Array

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Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

Fast Switching Activity Estimation for HLS-Produced Dataflow...

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international conference on field programmable logic and applications

作者： Jiantao Liu Maksymilian Graczyk Andrea Guerrieri Lana Josipović Department of Information Technology and Electrical Engineering ETH Zurich Zurich Switzerland EPFL School of Computer and Communication Sciences Lausanne Switzerland HES-SO School of Engineering Sion Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction level they operate on typically contains no or limited information on low-level circuit details that power consumption depends on. Dataflow circuits have recently been explored in the HLS context; apart from their ability to achieve performance that is superior to standard HLS-generated circuits, their well-defined structure and computational model offer entirely new opportunities for reasoning about power at the HLS level. This paper exploits this insight to present an accurate switching activity estimator for HLS-produced dataflow circuits. Our estimator combines the knowledge about the dataflow circuit structure with software profiling and detailed glitching analysis to estimate the circuit’s switching activity with an average error rate of 1.8% and average speedup of $17.8 \times$ compared with a cycle-accurate simulator. Our technology-agnostic solution makes a critical advancement in HLS power estimation and sets the stage for integrating power optimization within the HLS process.

关键词： Measurement Accuracy Power demand Estimation Hardware Software logic Optimization Standards Switching circuits

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Retcon: Live Updates for Embedded Event-Driven applications 23

Retcon: Live Updates for Embedded Event-Driven Applications

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23rd ACM/IEEE international conference on Information Processing in Sensor Networks, IPSN 2024

作者： Watson, Jean-Luc Agrawal, Saharsh Tsang, Ryan Luo, Sherry Popa, Raluca Ada Dutta, Prabal University of California Berkeley United States

ISBN: (纸本)9798350362015

Embedded systems are deeply integrated into critical applications but, despite their importance, lack an effective means to apply over-the-air software patches without significant downtime. Standard mechanisms for firmware updates require device reboots that wipe important in-memory state. Prior efforts have proposed "live"updates to address this problem, applying patches to an embedded application without a reset, but they tackle a limited set of applications or propose a clean-slate design. In this paper, we present Retcon, a live update toolchain for embedded systems that supports a familiar event-driven programming model and does not require application code changes. Retcon leverages static analysis at compile time to determine when it will be safe to update a device. To find safe update points in the presence of complex asynchronous behavior, we define a novel system state, asynchronous quiescence, in which an update can be applied. We evaluate Retcon on a set of embedded event-driven applications - a dual-chamber pacemaker model, a programmable logic controller runtime, an artificial pancreas system, and a sensing node - and demonstrate Retcon's ability to make low-overhead updates in less than one millisecond. © 2024 IEEE.

关键词： Embedded systems

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A Control System for Atomic Fountain Clock Based on field- programmable Gate Array

A Control System for Atomic Fountain Clock Based on Field- P...

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2023 Joint conference of the European Frequency and Time Forum and IEEE international Frequency Control Symposium, EFTF/IFCS 2023

作者： Liu, Dandan Ruan, Jun Fan, Sichen Zhang, Hui Bai, Yang Wang, Xinliang Shi, Junru Guan, Yong Zhang, Shougang Chinese Academy of Science National Time Service Center Xi'an710600 China University of Chinese Academy of Sciences Beijing100039 China Chinese Academy of Sciences Key Laboratory of Time and Frequency Primary Standards Xi'an710600 China

ISBN: (纸本)9798350311426

A control hardware for atomic fountain clock based on a field programmable gate array(FPGA) is presented, which can output 20 digital transistor-to-transistor logic(TTL) signals with resolution of 40 ns, 10 arbitrary waveforms and acquire 8 analog signals. Both outputs share same reference clock and trigger signal which ensures that all output signals are output in a synchronized well controlled way with a maximum timing error 500 ns. Moreover, The data acquisition and clock servo function is also integrated on FPGA. FPGA communicates with a PC by Ethernet. All the data are saved at the PC. © 2023 IEEE.

关键词： arbitrary waveforms atomic fountain clock clock servo control hardware FPGA

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Design of a Ping-Pong Game Machine Based on VHDL Language

Design of a Ping-Pong Game Machine Based on VHDL Language

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2023 IEEE international conference on Sensors, Electronics and Computer Engineering, ICSECE 2023

作者： Yinuo, Liu Yasong, Zhu Ying, Wang Dalian University of Technology School of Electronics and Automation City Institute Dalian China

ISBN: (纸本)9798350313734

This paper introduces the design of a digital frequency meter using EDA technology, written in Verilog HDL language and simulated with waveform diagrams, and finally completes the design of the top-level file. FPGA, as a programmable logic device, has been widely used in the fields of communication, aviation, medicine, and other fields due to its short development period, low cost, low power consumption, and high reliability. In order to explore more possibilities of FPGA in the field of home entertainment, greater practicality in the gaming industry, and greater macro opportunities in development and application, this paper proposes a Ping-Pong game machine that uses an FPGA chip as the control core and adds a small amount of peripheral circuitry. The game features simple and flexible operation, rich and practical functions, and can meet the needs of different users. It can also be promoted and popularized as a new form of entertainment. VHDL, as a hardware description language for high-speed integrated circuits, is widely used in various standardized hardware description languages for design automation tools. The core goal of this paper is to conceive and implement a Ping-Pong game machine. Through analysis, simulation, and optimization of the game process and related algorithms, the design scheme is finally determined. The knowledge about digital circuits and VHDL language is integrated to form a comprehensive knowledge system, which can basically realize the function of the Ping-Pong game machine and effectively simulate actual Ping-Pong games [1]. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs

A Software-Programmable Neural Processing Unit for Graph Neu...

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international conference on field programmable logic and applications

作者： Taikun Zhang Andrew Boutros Sergey Gribok Kwadwo Boateng Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada Programmable Solutions Group Intel Corporation

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require real-time low latency inference. Most existing GNN accelerators rely on preprocessing input graphs on a host/embedded CPU to parallelize computations on different sub-graphs, making them unsuitable for real-time use cases. Others are extremely specialized streaming pipelines for only a specific type of GNN and therefore suffer from long FPGA bitstream compile times when the model is updated and cannot be used in applications that combine GNNs with other classes of DL models. In this work, we enhance the neural processing unit (NPU) FPGA overlay architecture, instruction set, and software stack to support a variety of GNN models. We achieve this without sacrificing the NPU flexibility; our enhanced NPU can be programmed purely through software to accelerate different GNNs or any of its originally supported DL workloads (e.g. MLPs, RNNs, GRUs, LSTMs). In addition, this flexibility enables our NPU software compiler to generate GNN kernels with different performance targets (throughput-optimized vs. latency-optimized) by exploiting different dimensions of compute parallelism on the same overlay architecture. Besides the flexibility benefits, our NPU implemented on an Intel Stratix 10 NX (14 nm) FPGA can process $7.8 \times$ more graphs per second at a similar latency on average compared to a state-of-the-art model-specific FPGA accelerator targeting real-time applications on an AMD Ultrascale+ same-generation FPGA. It also achieves 5.8 $\times$ higher throughput compared to an Nvidia RTX A6000 GPU (8 nm) and $2.6 \times$ lower latency than a state-of-the-art accelerator that combines CPU-based graph preprocessing with AMD Versal (7 nm) fabric and AI engine compute. Finally, we present a case study for using our enhanced NPU in real-time GNNbased multi-input

关键词： Computational modeling Data preprocessing Full stack Computer architecture Throughput Graph neural networks Real-time systems Software Vectors field programmable gate arrays

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Wearable FPGA Platform for Accelerated DSP and AI applications

Wearable FPGA Platform for Accelerated DSP and AI Applicatio...

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IEEE international conference on Pervasive Computing and Communications (PerCom)

作者： Roggen, Daniel Cobden, Robert Pouryazdan, Arash Zeeshan, Muhammad Univ Sussex Wearable Technol Lab Brighton E Sussex England

ISBN: (纸本)9781665416474

Some algorithms benefit from a hardware digital logic implantation to achieve higher speed or to meet specific timing requirements, such as in digital signal processing, digital communication, and also when investigating hardware-accelerated machine learning algorithms. We present an extensible, miniature, battery-operated field programmable Gate Array (FPGA) platform for wearable computing and IoT research, based on an Intel MAX10 FPGA. The platform is 30x30mm in size and can be used as a standalone device, or as an extension to a similarly sized microcontroller board, for example to pre-process high-speed data streams in hardware prior to relaying the data to a conventional processor. We present the FPGA board and characterise power consumption, resource usage, and processing speed for the implementation of elementary DSP operations, notably FIR filters. We also carry out a direct comparison of these metrics for the FIR algorithm running on an ARM Cortex M4 processor as well as a soft-core processor synthesized on the FPGA board. The results show that this miniature FPGA platform has sufficient logic gates and computing power for a wide class of digital communication algorithms. The platform hardware and firmware is available on GitHub.

关键词： Wearable computing FPGA embedded computing IoT digital signal processing

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Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA

Fitop-Trans: Maximizing Transformer Pipeline Efficiency thro...

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international conference on field programmable logic and applications

作者： Kejia Shi Manting Zhang Keqing Zhao Xiaoxing Wu Yang Liu Jun Yu Kun Wang School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Recent years have witnessed Transformers emerge as a groundbreaking innovation in the Natural Language Processing (NLP) field. Unlike Recurrent Neural Network (RNN) models, Transformers process sequences in parallel, boosting accuracy for longer sequences. However, Transformers face challenges with extended processing time. This is particularly due to the requirement of padding inputs to match the longest sentence in a batch, thereby increasing computational demands. In this paper, we present Fitop-Trans, the first algorithm-hardware co-optimized framework using Fixed-Length Token Pruning strategy while deploying Transformers on FPGA. At the algorithmic level, we propose Fixed-Length Token Pruning. It is a novel pruning method which can maximize hardware efficiency in attention computation, aimed at eliminating unimportant tokens before the first layer. On the hardware side, a token selector is designed for Fixed-Length Token Pruning, which minimizes off-chip memory traffic. In addition, a partitionable Systolic Array (SA) is adopted, which is capable of handling varying input lengths and maximizing Digital Signal Processor (DSP) resource utilization. Furthermore, a scheduling module is designed to optimize hardware resource allocation and enhance pipeline attention throughput. Experimental results reveal that our hardware design on FPGA achieves a speedup of $580 \times$ and $6.39 \times$ in latency compared to Intel Xeon Gold CPU and NVIDIA GeForce RTX 3090.

关键词： Gold Recurrent neural networks Processor scheduling Pipelines Signal processing algorithms Transformers Hardware Natural language processing Resource management field programmable gate arrays

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FastCaps: A Design Methodology for Accelerating Capsule Network on field programmable Gate Arrays

FastCaps: A Design Methodology for Accelerating Capsule Netw...

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international Joint conference on Neural Networks (IJCNN)

作者： Rahoof, Abdul Chaturvedi, Vivek Shafique, Muhammad Indian Inst Technol Palakkad Palakkad India New York Univ Abu Dhabi U Arab Emirates

ISBN: (纸本)9781665488679

Capsule Network (CapsNet) has shown significant improvement in understanding the variation in images along with better generalization ability compared to traditional Convolutional Neural Network (CNN). CapsNet preserves spatial relationship among extracted features and apply dynamic routing to efficiently learn the internal connections between capsules. However, due to the capsule structure and the complexity of the routing mechanism, it is non-trivial to accelerate CapsNet performance in its original form on field programmable Gate Array (FPGA). Most of the existing works on CapsNet have achieved limited acceleration as they implement only the dynamic routing algorithm on FPGA, while considering all the processing steps synergistically is important for real-world applications of Capsule Networks. Towards this, we propose a novel two-step approach that deploys a full-fledged CapsNet on FPGA. First, we prune the network using a novel Look-Ahead Kernel Pruning (LAKP) methodology that uses the sum of look-ahead scores of the model parameters. Next, we simplify the non-linear operations, reorder loops, and parallelize operations of the routing algorithm to reduce CapsNet hardware complexity. To the best of our knowledge, this is the first work accelerating a full-fledged CapsNet on FPGA. Experimental results on the MNIST and F-MNIST datasets (typical in Capsule Network community) show that the proposed LAKP approach achieves an effective compression rate of 99.26% and 98.84%, and achieves a throughput of 82 FPS and 48 FPS on Xilinx PYNQ-Z1 FPGA, respectively. Furthermore, reducing the hardware complexity of the routing algorithm increases the throughput to 1351 FPS and 934 FPS respectively. As corroborated by our results, this work enables highly performance-efficient deployment of CapsNets on low-cost FPGA that are popular in modern edge devices.

关键词： Capsule Network Neural Network Pruning FPGA Hardware Accelerator Deep Learning

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