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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16720 条记录，以下是441-450 订阅

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HLS_Profiler: Non-Intrusive Profiling tool for HLS based applications 22

HLS_Profiler: Non-Intrusive Profiling tool for HLS based App...

引用

13th Annual ACM/SPEC international conference on Performance Engineering (ICPE)

作者： Sumeet, Nupur Deeksha Nambiar, Manoj Tata Consultancy Serv Res Mumbai Maharashtra India

ISBN: (纸本)9781450391597

The High-Level Synthesis (HLS) tools aid in simplified and faster design development without familiarity with Hardware Description Language (HDL) and Register Transfer logic (RTL) design flow that can be implemented on an FPGA (field programmable Gate Array). However, it is not straight forward to trace and link source code to synthesized hardware design. On the other hand, the traditional RTL-based design development flow provides the fine-grained performance profile through waveforms. With the same level of visibility in HLS designs, the designers can identify the performance-bottlenecks and obtain the target performance by iteratively fine-tuning the source code. Although, the HLS development tools provide the low-level waveforms, interpreting them in terms of source code variables is a challenging and tedious task. Addressing this gap, we propose to demonstrate an automated profiler tool, HLS_Profiler, that provides a performance profile of source code in a cycle-accurate manner.

关键词： Hardware profiling HLS Designs Performance Profile Performance Analysis

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LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization

LORA: A Latency-Oriented Recurrent Architecture for GPT Mode...

引用

international conference on field programmable logic and applications

作者： ZhenDong Zheng Qianyu Cheng Teng Wang Lei Gong Xianglan Chen Cheng Tang Chao Wang Xuehai Zhou School of Computer Science and Technology Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Large Language Models (LLMs) have been widely deployed in data centers to provide various services, among which the most representative is the Generative Pre-trained Transformer (GPT). The GPT model has heavy memory and computing overhead, and its inference process has two stages with distinct computing characteristics: Prefill and Decode. Utilizing existing GPUs and FPGA accelerators to construct a platform for deploying GPT in data centers faces the challenges of needing more effective synchronization schemes or structures with higher computational intensity. This paper proposes LORA, a low latency end-to-end GPT acceleration platform utilizing multiple FPGAs. Firstly, we optimize the synchronization timing of the GPT model to reduce the computation and communication overhead. Secondly, we devise some efficient synchronization steps for specific layers of the GPT model that overlap part of the computation and communication delay to improve the latency of our platform. Finally, we deploy recurrent structures on each FPGA to accelerate the different stages of the GPT model. Implemented on the Xilinx Alveo U280 FPGAs, LORA achieves an average $11.1 \times$ speedup over NVIDIA V100 GPUs on the modern GPT-2 model. Compared to the existing multi-FPGA accelerator appliance, LORA shows performance improvements of up to $4 \times$ and $2.7 \times$ in the Prefill and Decode stages.

关键词： Data centers Computational modeling LoRa Prototypes Transformers Data models Synchronization Low latency communication field programmable gate arrays Optimization

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Order Analysis Algorithm Based on Time-Domain Stretching and Its logic Implementation 16

Order Analysis Algorithm Based on Time-Domain Stretching and...

引用

16th IEEE international conference on Electronic Measurement and Instruments, ICEMI 2023

作者： Wei, Yangbin Li, Hao Cao, Jiawei Luo, Guangkun Li, Xuyang Wang, Zhigang School of Automation Engineering University of Electronic Science and Technology of China Chengdu China

ISBN: (纸本)9798350327144

To address the spectrum aliasing caused by the non-uniform and non-stationary characteristics of rotating machinery vibration signals in the field of dynamic signal analysis, this paper proposes a time-domain stretching based order analysis algorithm. This algorithm stretches the vibration signal in the time domain, which facilitates the frequency domain compression caused by the signal stretching in the time domain to reduce the frequency domain aliasing caused by the spectrum broadening caused by the characteristics of the vibration signal. At the same time, in order to deal with the unequal interval sampling caused by the signal stretching in time domain, this paper integrates the resampling principle of cubic spline interpolation into the algorithm, which improves the accuracy of order analysis. In addition, the implementation of this algorithm in field programmable Gate Array (FPGA) is described in detail. At the same time, this paper also uses simulation experiments to test each module inside the algorithm, and analyzes the accuracy of important steps such as cubic spline interpolation, which verifies the feasibility of the actual system. © 2023 IEEE.

关键词： Frequency domain analysis

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Comparison of Hardware Complexity of Multipliers GF(pm) 12

Comparison of Hardware Complexity of Multipliers GF(pm)

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12th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and applications, IDAACS 2023

作者： Zholubak, Ivan Hlukhov, Valeriy Muliarevych, Oleksandr Lviv Polytechnic National University Department of Computer Engineering Lviv79012 Ukraine

ISBN: (纸本)9798350358056

The article discusses the use of Galois field (GF) multipliers for cryptographic data protection based on elliptical curves. It recommends using extended Galois fields with characteristics d} > 2 for digital signatures. The article proposes a criterion for determining the best field to use for data protection. It also describes methods for creating cryptoprocessors cores, including a VHDL generator for extended Galois field multipliers. However, generating field multipliers with large characteristics can be time-consuming. To improve efficiency, the article suggests simplifying the design and minimizing logic gates in an FPGA. The article determines the best fields for data protection based on the selected criterion and a certain algorithm. © 2023 IEEE.

关键词： adder field characteristic IP core generator multiplier multiplier generator the order of the generating polynomial

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A Precision, High Intensity and programmable Current Power Supply for LED in Biomedical applications 9th

A Precision, High Intensity and Programmable Current Power S...

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9th international conference on the Development of Biomedical Engineering in Vietnam, BME 2022

作者： Ngoc Tran, Viet Thanh Nguyen, Qua Thi Thuy Le, Tien Khoi Pham, Nguyen Van Vo, Toi HCMC700000 Viet Nam

ISBN: (纸本)9783031446290

In Biomedical photonics, a precision current source with high intensity and programmable, which can generate pulses of variable frequencies, is necessary to drive devices such as LED or LED lasers. Such a source was built, and different applications in the biomedical field have been explored. The circuit consists of a power section providing sufficient power to the MOSFET for the generation of a current source of up to 15,000 mA, and the control section using an Op-Amp circuit with no feedback that controls the current level passing through the MOSFET and generates a pulse trigger for frequency control. Managing the input voltage of the Op-Amp circuit, a 16-bit DAC of the ARM Cortex-M3 was used. The current source was tested with a FLUKE current meter, and pulse duration was calibrated with a Tektronix Oscilloscope. The source can provide a continuous current of 0 mA – 2,000 mA with an accuracy of ±1 mA, and a continuous pulse current of 0 mA – 15,000 mA with an accuracy of ±4 mA. It can supply up to 30 V with a continuous current power of 60W and a pulse source power of 450 W. Moreover, the source can also generate current pulses with a duration from 10 µs with an error of ±0.5 µs to 200 ms with an error of ±0.5 ms. Single pulses and multiple pulses of variable frequencies can be generated as well. In inclusion, the source was used to drive LEDs successfully for imaging applications. Other applications in biomedical photonics have been sought. © The Author(s), under exclusive license to Springer Nature Switzerland AG. 2024.

关键词： Light emitting diodes

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IEC 61131-3 Software Testing - Automatic test generation for native applications 13

IEC 61131-3 Software Testing - Automatic test generation for...

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13th ACM/IEEE international conference on Cyber-Physical Systems (ICCPS )

作者： Hofer, Florian Free Univ Bolzano Bozen Bolzano BZ Italy

ISBN: (纸本)9781665409674

programmable logic Controllers (PLCs) are the most used digital systems in the manufacturing industry, but there is little support for testing such systems. Despite the recommendations of the IEC 61131-3 standards, testing is mainly done manually or not at all. Recent successful attempts for a testing framework for PLCs include proposals close to object orientation. This work presents a test generation approach using such a testing system. Via our Advanced POU Testing (APTest) Framework written in a native IEC 61131-3 - compliant language, we demonstrate the automatic generation and execution of unit tests for existing software units. We introduce the software, discuss its features, and demonstrate its use.

关键词： Control software IEC 61131-3 Automation Unit Test CoDeSys

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FPL Demo: Hot Reconfiguration - Partial Reconfiguration without Bounds

FPL Demo: Hot Reconfiguration - Partial Reconfiguration with...

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international conference on field programmable logic and applications

作者： Myrtle Shah Institute of Computer Engineering Heidelberg University DE

Traditionally, partial reconfiguration of FPGAs involves replacing defined regions of the design, entirely replacing the logic and losing the state within that region. However, configuration frame reloads typically being glitch free means that wires and logic can safely be added and removed at runtime, without losing state - potentially even without stopping the clock! This could even be extended into an “edit and continue” mode where register positions and unchanged logic is preserved, and only changed logic cones are replaced, to enable small design changes to be made to a live system with only a brief pause and no loss of state.

关键词： Runtime Wires Registers field programmable gate arrays Clocks

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Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Leveraging Dual Output LUTs with Pipelining for Efficient BC...

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international conference on VLSI Design

作者： Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. This paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. The utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.

关键词： Embedded systems Computer architecture Very large scale integration Throughput Table lookup logic field programmable gate arrays Adders Optimization Arithmetic

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Exploring Performance Trade-offs in Excess-3 to BCD Code Implementation on Zynq FPGA: A Power and Temperature Analysis 2

Exploring Performance Trade-offs in Excess-3 to BCD Code Imp...

引用

2nd international conference on Intelligent Cyber Physical Systems and Internet of Things (ICoICI)

作者： Singh, Gurdeep Kaur, Amanpreet Chitkara Univ Inst Engn & Technol Dept Elect & Commun Engn Rajpura Punjab India

ISBN: (纸本)9798331540661;9798331540678

Mostly focusing on the Zynq FPGA board, this effort targets energy-efficient green communication using FPGA devices. Examined in practical applications, excess-3 to binary coding is noted for its simplicity in digital system decimal number representation. The 1.364W Zynq FPGA board runs dynamic power at 1.236W and stationary power at 0.127W. Effective thermal control comes from its 40.7 degrees C junction temperature and 44.3 degrees C thermal margin. Using just 0.01% of its Look-Up Table (LUT) hardware and 4.0% of its Input/Output (IO) capability, the board maximizes resource use. These benchmarks show how well the Zynq FPGA board designs energy-efficient circuits required to solve world energy crises. Particularly in green communication technologies, the Zynq FPGA board with its economy and heat control offers potential for creating long-term digital solutions.

关键词： Vivado Xilinx Binary Code Excess 3 Code Zynq Genesys FPGA (field-programmable Gate Array) Energy efficient Power saving

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Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs

Leveraging HBM2 for Accelerating k-mer Counting with oneAPI ...

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international conference on field programmable logic and applications

作者： Owen P. Lucas Alan D. George NSF SHREC Center ECE University of Pittsburgh Pittsburgh USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Counting substrings of an arbitrary length k (k-mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data $(\gt100$ s of GBs per genome), which need to be processed using frequent memory accesses into data structures considerably larger than available cache, leading to a memorybound runtime. Stemming from the gap between processor and memory speed, this bottleneck requires alternative architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ high-capacity, high-bandwidth memory to address memory-bound tasks. This research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. The architecture was designed using Intel’s oneAPI, which enables high-level synthesis for FPGA programming. The accelerator architecture was able to leverage inherent parallelism in the algorithm via the multiple parallel hash functions, along with partitioning data structure across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. The accelerator achieved $42.67 \mathrm{M} \boldsymbol{k}$-mers per second, $2.80 \times$ more than the throughput-optimized CPU version and $4.31 \times$ more than the original CPU app. Despite this speedup, the architectures saw diminishing returns when attempting to incorporate additional HBM2 banks. OneAPI was able to achieve speedup over the CPU using the FPGA and emerging memory, but it’s somewhat limited in its current scaling capabilities.

关键词： Performance evaluation Hash functions Sequential analysis Pipelines Parallel processing logic gates Throughput System-on-chip Kernel field programmable gate arrays

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