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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16795 条记录，以下是4591-4600 订阅

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Generating Timing and Control Signals for C-Band T/R Module using FPGA

Generating Timing and Control Signals for C-Band T/R Module ...

引用

IEEE international conference on Recent Trends in Electronics, Information & Communication Technology

作者： Farooq Azam A. R. Karwankar Giridhar Isola Department of Electronics and Telecommunication Engineering Government College of Engineering Aurangabad Scientist E Atmospheric Radar and Instrumentation Division SAMEER IIT Powai

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

The main objective of this paper is to design FPGA based controller for C-band T/R Module. The T/R Module is the basic building block of phase array polarimetric weather radar. Phase array polarimetric radar have the different mode of operations and beam produces by the antenna can be steered electronically as compared to single target radars, conventionally used in defense and other applications. The various parameters like phase angle, attenuation, PRF and pulse width can be varied in accordance with the operational mode is implemented in Xilinx XC6SLX16-CSG324 Spartan 6 FPGA SP601.

关键词： T/R module controller FPGA spartan 6 SP601 UART MATLAB based GUI Universal Asynchronous Receiver Transmitter field programmable gate arrays TMEFF2 gene TRANSFORMER ROOM F2R gene Radar polarimetry basic component operational mode CONTROL SIGNAL PULSE WIDTH Electronics operation mode

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A Platform for Vehicular Networks in the Cloud to applications in Intelligent Transportation Systems 26

A Platform for Vehicular Networks in the Cloud to Applicatio...

引用

26th IEEE international conference on Enabling Technologies - Infrastructure for Collaborative Enterprises (WETICE)

作者： Leite Junior, George do Nascimentos, Rogerio P. C. Dantas, Mario A. R. de Macedo, Douglas D. J. Univ Fed Sergipe Postgrad Program Comp Sci PROCC Dept Comp Sci Aracaju Sergipe Brazil Univ Fed Santa Catarina Dept Informat Sci Florianopolis SC Brazil Univ Fed Santa Catarina Dept Comp Sci Florianopolis SC Brazil

ISBN: (纸本)9781538617595

Mobility is a major problem in urban centers and vehicular networks have been a focus of study in the attempt to create applications focused on intelligent transport systems (ITS). With that in mind, ITS initiatives act as a possible solution to improve the functioning and performance of traffic systems, reducing congestion and increasing security for citizens. In this way, the present work presents a flexible and extensible platform called i9Vanets, whose objective is the virtualized management through a cloud vehicular network to assist in the solutions of the main challenges related to VANETs. An analysis of laboratory tests is also presented, with the objective of evaluating their performance and operational capacity. Thus, the conclusion of this work was to present the I9Vanet platform and its technical feasibility as well as its possible applications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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BLEB : Bluetooth Low Energy Botnet for large scale individual tracking 1

BLEB : Bluetooth Low Energy Botnet for large scale individua...

引用

1st international conference on Next Generation Computing applications (NextComp)

作者： Issoufaly, Taher Tournoux, Pierre Ugo Univ Reunion Isl Lab Informat & Math 2 Rue Joseph Wetzell St Denis Reunion France

ISBN: (纸本)9781538638316

This paper consider the problem of tracking user through the wireless fingerprint of their network interfaces. Bluetooth Low Energy (BLE) is one of these network interfaces and becomes more and more popular because of its energy efficiency and its improved security. The use of random MAC addresses and deep changes in the bluetooth communication procedure were expected to prevent the tracking of individuals through the BLE devices they carries. We reviewed popular devices and found that privacy preserving MAC address are rarely used, even when considering ubiquitous devices that are carried by users all the time. Combined with the new advertising procedure introduced in BLE, this constitute a serious flaw that can be used to track individuals. We investigate its exploitation by BLEB, a BLE Botnet comprise of smartphone and portable devices compromised by a tracking adversary. We investigate the multiple ways to implement it and show that with limited effort, an adversary using BLEB can achieve large scale, high precision and stealthy tracking. A BLEB attack can be more privacy threatening than the ones carried through WiFi or classic bluetooth during their early deployment.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Modular One-to-many Clutchable Actuator for a Soft Elbow Exosuit

Modular One-to-many Clutchable Actuator for a Soft Elbow Exo...

引用

international conference on Rehabilitation Robotics (ICORR)

作者： Canesi, M. Xiloyannis, M. Ajoudani, A. Bicchi, A. Masia, L. Univ Pisa Res Ctr E Piaeeio Robot Grp Pisa Italy Nanyang Technol Univ Robot Res Ctr Mech & Aerosp Engn Singapore Singapore Ist Italiano Tecnol Human Robot Interfaces & Phys Interact Lab Genoa Italy Italian Inst Technol SoltRobot Lab Human Cooperat & Rehabil Genoa Italy

ISBN: (纸本)9781538622964

Exoskeletons have been developed for a wide range of applications, from the military to the medical field, with the aim of augmenting human performance or compensating for neuromuscular deficiencies. However, to empower the high number of degrees of freedom of the human body, they often employ a high number of motors, increasing the size, weight and power consumption of the system. We hereby present an actuation strategy to empower our elbow exosuit that adopts a single motor to drive multiple, independently actuated, degrees of freedom. This paradigm, known as One-to-many, is achieved using a modular design where each module comprises a clutchable mechanism that allows to convert a single directional motion from the prime mover to a selectable bidirectional output. Moreover, the mechanism has a locking feature that enables the wearer of the exoskeleton to hold a static load with a minimal power consumption. We present a simple controller for the clutchable unit based on a finite-state machine model, and evaluate its performance for varying input velocities. The system is shown to have a bandwidth of 1.5 Hz, sufficient for daily elbow movements, whilst retaining a compact design.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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3D Packaging Challenges for High-End applications 67

3D Packaging Challenges for High-End Applications

引用

IEEE 67th Electronic Components and Technology conference (ECTC)

作者： Agarwal, Rahul Kannan, Sukeshwar England, Luke Reed, Rick Song, Yong Lee, WangGu Lee, SangHyoun Yoo, JinKun GLOBALFOUNDRIES Malta NY 12020 USA AMD Sunnyvale CA 94088 USA Amkor Technol Chandler AZ USA Amkor Technol Seoul South Korea

ISBN: (纸本)9781509063154

In this paper, the processing and integration challenges addressed during the 3D packaging of a similar to 400 mm(2) logic die are presented and discussed. The logic die was fabricated using GLOBALFOUNDRIES' 14-nm technology with 5x55 mu m Through Silicon Vias (TSVs) integrated in the process as a via middle flow [1]. Fully fabricated test wafers were thinned down to 50 mu m, using Amkor Technology's Middle End of Line (MEOL) process and TSVs were revealed [2]. Device performance was measured before and after thinning to validate no shift in performance. Wafers were diced and assembly performed on a multilayer laminate using flip chip bonding with a mass reflow process for both bottom and top die. Warpage control ensured that 100% wetting was achieved. Two top dies (mechanical High Bandwidth Memory (HBM) dies) were assembled on this stack using micropillars. A novel machined lid was designed to fit the package and improve thermal performance of the package. Simulation data of the lid design showing the thermal improvement is presented. Finally, the packages were tested after three-dimensional (3D) assembly, and the T0 assembly yield data is presented.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer 26

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultras...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Simon, W. Yuzuguler, A. C. Ibrahim, A. Angiolini, F. Arditi, M. Thiran, J. -P. De Micheli, G. Ecole Polytech Fed Lausanne CH-1015 Lausanne Switzerland Univ Hosp Ctr CHUV Dept Radiol Lausanne Switzerland Univ Lausanne UNIL Lausanne Switzerland

ISBN: (纸本)9782839918442

We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. The design has been demonstrated for a 32 x 32-channel receive probe, and we extrapolated the requirements of the architecture for 80 x 80 channels.

关键词： field programmable gate arrays (FPGA)

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Multi-context scrubbing method 60

Multi-context scrubbing method

引用

60th IEEE international Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Fujimori, Takumi Watanabe, Minoru Shizuoka Univ Elect & Elect Engn 3-5-1 Johoku Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9781509063895

Two salient concerns of current field programmable gate arrays (FPGAs) used for space applications are how to block soft errors that arise on their configuration memories and how to treat permanent failures attributable to total dose effects. To date, those two main concerns have been treated separately, but we present a proposal for multi-context scrubbing to "kill two birds with one stone" and resolve both issues simultaneously. To decrease the frequency of soft errors arising on the configuration memories of FPGAs, applying scrubbing operations for configuration memories is extremely useful. Since faster scrubbing can increase the radiation tolerances of the configuration memories on FPGAs, optical high-speed scrubbing using optically reconfigurable gate array (ORGA) architecture is introduced. Up to now, major scrubbing operations have invariably used a single configuration context, but since the storage capacities of holographic memories on ORGAs are high, many configuration contexts can be stored on a holographic memory. Thereby, various configuration contexts that avoid permanent failures can be used cyclically for scrubbing operations. Even if a permanent failure occurs on the programmable gate array during scrubbing operations, which exploit numerous configuration contexts, correct operations can be executed.

关键词： Space applications

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Analyzing Operational Behavior of Stateful Protocol Implementations for Detecting Semantic Bugs 47

Analyzing Operational Behavior of Stateful Protocol Implemen...

引用

47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： Hoque, Endadul Chowdhury, Omar Chau, Sze Yiu Nita-Rotaru, Cristina Li, Ninghui Purdue Univ W Lafayette IN 47907 USA Univ Iowa Iowa City IA USA Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781538605424

Network protocol implementations must comply with their specifications that include properties describing the correct operational behavior of the protocol in response to different temporal orderings of network events. Due to inconsistent interpretations of the specification, developers can unknowingly introduce semantic bugs, which cause the implementations to violate the respective properties. Detecting such bugs in stateful protocols becomes significantly difficult as their operations depend on their internal state machines and the complex interactions between the protocol logic. In this paper, we present an automated tool to help developers analyze their protocol implementations and detect semantic bugs violating the temporal properties of the protocols. Given an implementation, our tool (1) extracts the implemented finite state machine (FSM) of the protocol from the source code by symbolically exploring the code and (2) determines whether the extracted FSM violates given temporal properties by using an off-the-shelf model checker. We demonstrated the efficacy of our tool by applying it on 6 protocol implementations. We detected 11 semantic bugs (2 with security implications) when we analyzed these implementations against properties obtained from their publicly available specifications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Partial Reconfiguration Controller for Altera Stratix V FPGAs 26

A Partial Reconfiguration Controller for Altera Stratix V FP...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Xiao, Zhenzhong Koch, Dirk Lujan, Mikel Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9782839918442

With the introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigurable regions can be arbitrarily defined which is possible by writing a configuration mask prior to writing the actual configuration data to the FPGA fabric. In this paper, we will present details and the flow for implementing partial reconfiguration using Altera FPGAs, as well as a study on configuration bitstream sizes and configuration speeds for various resource and bounding-box aspect ratio variants. The results are used to build a partial reconfiguration controller that is featuring a lightweight but effective bitstream decompression module for greatly improving configuration speed on a DE5-net board.

关键词： field programmable gate arrays (FPGA)

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A Novel Transformerless Asymmetrical Fifteen Level Inverter Topology for Renewable Energy applications

A Novel Transformerless Asymmetrical Fifteen Level Inverter ...

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international conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)

作者： S. Chaitanya N. Rajanand Patnaik Ch. B. A. Raju Department of EEE Govt Engg College Bharatpur India G. S. Electricals Vijayawada AP India Department of EEE AEC Kakinada Surampalem India

In the field of medium and high power applications Multilevel Inverter (MLI) topology is an alternative concept. It has the capability to generate the high voltage staircase pseudo-sinusoidal waveform with less distortion and high quality. But it requires more number of Switching Components (SC) with complex PWM (Pulse Width Modulation) strategies hence the cost and size of inverter becomes high. So, in view of this authors investigated a novel asymmetrical transformerless MLI topology of fifteen level inverter is presented in this paper, with an attempt of reduction in overall device count (switches, diodes, capacitors, dc voltage sources, etc.,) compared to all existing multilevel inverters. The basic structure and operating modes of proposed MLI is explained clearly. It requires seven power switches (IGBT), three diodes and three DC-bus capacitors are required to generate fifteen level 1-Φ voltage. Furthermore, an efficient PWM technique is implemented with seven reference signals whose magnitude is equal to carrier signal. The performance of proposed MLI is accomplished in terms of Total Harmonic Distortion (THD) at modulation index M=0.9. The evaluation of MLI is carried out through MATLAB/SIMULINK environment.

关键词： Inverters logic gates Topology Pulse width modulation Capacitors Switches Harmonic analysis

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